User`s guide

LZ87010 Advance User’s Guide 8051-Compatible Core
1/15/03 3-3
3.2.4 DPS (Data Pointer Select) Register
The DPS (Data Pointer Select) register determines whether the DPL/DPH or DPL1/DPH1
register pairs are used as the 16-bit DPTR register. It also contains the bit that determines
whether opcode 0xA5 is the TRAP or the ‘MOVC @(DPTR++),A’ (program memory write)
instruction.
Table 3-6. DPS Register
BIT 7 6 5 4 3 2 1 0
FIELD /// /// /// TRAP_EN /// /// /// DPSEL
RESET 000 0 0 000
RW RO RO RO RW RO RO RO RW
ADDR 0x86
Table 3-7. DPS Register Bits
BIT NAME DESCRIPTION
7:5 /// Reserved Reads return ‘0’; write as ‘0’.
4 TRAP_EN
Trap Enable If ‘1’, opcode 0xA5 functions as the TRAP (software breakpoint)
instruction. If ‘0’, opcode 0xA5 functions as the ‘MOVC @(DPTR++),A’ instruction
3:1
/// Reserved Reads return ‘0’; write as ‘0’.
0 DPSEL
Data Pointer Select Selects which register pair forms the 16-bit DPTR register:
0 = DPTR is taken from DPL and DPH
1 = DPTR is taken from DPL1 and DPH1