User`s guide

Internal Flash LZ87010 Advance User’s Guide
5-2 1/15/03
5.1.2 Flash Timing
Timing of individual Flash operations is controlled by the Flash controller. In normal (read-
only) operation, Flash reads have no wait states. When writing is enabled, reads have two
wait states.
During programming and erasure, the Flash controller generates processor wait states to
prevent access to the Flash while an operation is in progress.
To accommodate different system clock frequencies, a Flash timebase register (FLASHTB)
must be set up to the number of HFCLK cycles in a 5
µs period, minus one. For example,
at a 40 MHz crystal, there are 200 HFCLK cycles in 5
µs, so the FLASHTB register would
be programmed to 199 (decimal).
The FLASHTB register can only be set when the clock divider in CLKCFG.CLKDIV is
0b000 (which sets the clock divider to 1). If the clock divider is subsequently changed, the
Flash controller will adjust its internal copy of FLASHTB to maintain consistent timing.
The Flash controller does not scale its timing when the 32 kHz SUBCLK is used as the
system clock. The Flash should not be written under these circumstances.
Write timing varies according to the type of operation, as shown in Table 5-1.
5.1.3 Secure Mode
Secure Mode prevents the downloading or partial modification of the contents of Flash
memory, to protect the software from copying, reverse-engineering, or tampering. Secure
Mode can be exited by mass erasing the entire Flash.
In Secure Mode, the following restrictions apply:
• Data writes to Flash memory are ignored
• Sector Erase requests are ignored
• The Flash memory cannot be read via the Debug Interface
• External memory is disabled by forcing the XMCFG.XMALL bit to ‘1’.
Secure Mode is entered automatically on Reset if the last byte of the Info Array contains 0x55.
Table 5-1. Approximate Flash Timing
Timing Parameter Value
Byte Write Time 20 - 40 µs
Sector Erase Time 10 ms
Mass Erase Time 200 ms