User`s guide

Table of Contents LZ87010 Advance User’s Guide
iv 1/15/03
Chapter 8 – Enhanced Timers
8.1 Enhanced Timer Signals .................................................................................. 8-3
8.2 Enhanced Timer Theory of Operation .............................................................. 8-3
8.2.1 Reading 16-bit Timer Registers................................................................. 8-3
8.2.2 Writing 16-bit Timer Registers ................................................................... 8-4
8.2.3 Timer Clocking .......................................................................................... 8-5
8.2.4 Timing and Counting ................................................................................. 8-5
8.2.5 Capture...................................................................................................... 8-5
8.2.6 Compare.................................................................................................... 8-8
8.2.7 PWM........................................................................................................ 8-11
8.2.8 Timer Interrupts ....................................................................................... 8-13
8.3 Enhanced Timer Registers.............................................................................8-14
8.3.1 T2CAP and T3CAP (Capture Control) Registers .................................... 8-14
8.3.2 T(x)CAP(y) (Captured Data) Registers ................................................... 8-15
8.3.3 T(x)CMP (Compare Control) Registers ................................................... 8-17
8.3.4 T(x)CMP[1:0][H:L] (Compare Data) Registers......................................... 8-18
8.3.5 T(x)CNTH and T(x)CNTL (Timer Count) Registers ................................. 8-19
8.3.6 T(x)CON (Timer Configuration) Registers ............................................... 8-20
8.3.7 T(x)STA (Timer Status) Registers ........................................................... 8-21
8.3.8 TCMPOE (Timer Compare Output Enable) Register ..............................8-22
Chapter 9 – Watchdog Timer
9.1 Theory of Operation ......................................................................................... 9-1
9.1.1 Setting the Timer Interval .......................................................................... 9-1
9.1.2 Stopping the Watchdog Timer in Idle Mode .............................................. 9-2
9.2 Watchdog Timer Registers............................................................................... 9-2
9.2.1 WDTCTL Register ..................................................................................... 9-2
9.2.2 WDTCNT Register .................................................................................... 9-3
Chapter 10 – UARTs
10.1 Theory of Operation .....................................................................................10-1
10.1.1 Receive Operation................................................................................. 10-1
10.1.2 Transmit Operation................................................................................ 10-3
10.1.3 Generating Baud Rates ......................................................................... 10-6
10.1.3.1 Mode 0............................................................................................ 10-8
10.1.3.2 Modes 1 and 3................................................................................ 10-8
10.1.3.3 Mode 2............................................................................................ 10-9
10.1.3.4 Crystal Selection for RS-232 Baud Rates ...................................... 10-9
10.1.4 Serial Interrupts ................................................................................... 10-10
10.2 Signals........................................................................................................ 10-11
10.3 UART Registers ......................................................................................... 10-11
10.3.1 SCON and SCON1 (Serial Control) Registers .................................... 10-11
10.3.2 SBUF and SBUF1 (Serial Data Buffer) Registers ............................... 10-13
10.3.3 BRGCNTH and BRGCNTL (Baud Rate Generator Count) Registers . 10-14