User`s guide

LZ87010 Advance User’s Guide Internal Flash
1/15/03 5-3
5.2 Registers
5.2.1 FLASHCFG (Flash Configuration) Register
The FLASHCFG register configures the operating mode of the Flash memory and deter-
mines whether the Info Array is visible or not.
Table 5-2. FLASHCFG Register
BIT 7 6 5 4 3 2 1 0
FIELD SECURE /// FMAP FMOD[4] FMOD[3] FMOD[2] FMOD[1] FMOD[0]
RESET 0 0 000001
RW RO RW RW RW RW RW RW RW
ADDR 0x96
Table 5-3. FLASHCFG Register Bits
BIT NAME DESCRIPTION
7 SECURE
Secure Mode This read-only bit is ‘1’ if the Flash controller is in Secure Mode.
Secure Mode is entered on Reset if the last byte of the Info Array is 0x55. Se-
cure Mode can be exited by Mass Erasing the Flash. In Secure Mode, byte
writes and sector erasure is not allowed, nor is reading the Flash over the De-
bug Interface.
6 /// Reserved Returns ‘0’, write as ‘0’.
5FMAP
Flash Memory Map If ‘0’, the main 64KB Data Array occupies the entire Flash
memory space. If ‘1’, the Info Array replaces the upper 128 bytes of the Data
Array (addresses 0xFF80-0xFFFF).
4:0 FMOD
Flash Mode Selects between Normal, Program, Sector Erase, and Mass
Erase modes. See Table 5-4.
Table 5-4. FMOD Field Decoding
FMOD[4:0] DESCRIPTION
0b00001
Normal (Read-Only) Access Mode
0b00010 Reserved
0b00100
Program Mode Writes to the Flash are allowed. Note that in Program Mode,
reads have 2 wait states. In all other modes, they have no wait states.
0b01000
Sector Erase Mode Writes perform Sector Erase cycle on the 512-byte sector
containing the address written.
0b10000 Mass Erase Mode Writes trigger a Mass Erase cycle.