User`s guide

Internal Flash LZ87010 Advance User’s Guide
5-4 1/15/03
5.2.2 FLASHTB (Flash Timebase) Register
The FLASHTB (Flash timebase) register calibrates the Flash controller relative to the
system clock, so the time-sensitive Flash operations can take place accurately.
Table 5-5. FLASHTB Register
BIT 7 6 5 4 3 2 1 0
FIELD FTB[7] FTB[6] FTB[5] FTB[4] FTB[3] FTB[2] FTB[1] FTB[0]
RESET 0 1 100011
RW RW RW RW RW RW RW RW RW
ADDR 0x97
Table 5-6. FLASHTB Register Bits
BIT NAME DESCRIPTION
7:0 FTB
Flash Timebase For proper Flash timing on Write and Erase cycles, this field
must be set to the number of HFCLK periods (minus 1) that occur in a 5 µs period.
For example, with a HFCLK of 40 MHz, there are 200 HFCLK cycles in 5 ms, so
the FTB field should be set to 199 (decimal).
Note that this register is read/write only when the system clock divisor is 1
(CLKCFG.CLKDIV = 0). It is read-only otherwise. The Flash controller will
compensate by scaling its timing automatically whenever the CLKCFG.CLKDIV
field is updated.