User`s guide

8051-Compatible Timers LZ87010 Advance User’s Guide
7-6 1/15/03
7.2 Timer 0 and Timer 1 Signals
7.3 Timer 0 and 1 Registers
7.3.1 TCON (Timer 0 and 1 Control) Register
Table 7-1. Timer 0 and Timer 1 I/O
NAME DIRECTION DESCRIPTION
CTIN0 In External clock input, Timer 0
CTIN1 In External clock input, Timer 1
EXT0 In Clock enable/disable, Timer 0
EXT1 In Clock enable/disable, Timer1
Table 7-2. TCON Register
BIT 7 6 5 4 3 2 1 0
FIELD TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
RESET 0 0 000000
RW RW RW RW RW RW RW RW RW
ADDR 0x88*
Table 7-3. TCON Register Bits
BIT NAME DESCRIPTION
7 TF1
Timer 1 Overflow Set automatically by the timer hardware when Timer 1 over-
flows (that is, when it goes from all ‘1’ bits to all ‘0’ bits). Cleared automatically when
the processor calls the Timer 1 interrupt service routine.
6TR1Timer 1 Run Control The timer runs if this bit is set and stops if it is cleared.
5 TF0
Timer 0 Overflow Set automatically by the timer hardware when Timer 0 over-
flows (that is, when it goes from all ‘1’ bits to all ‘0’ bits). Cleared automatically when
the processor calls the Timer 0 interrupt service routine.
4TR0Timer 0 Run Control The timer runs if this bit is set and stops if it is cleared.
3IE1
Interrupt Edge 1 (Not timer-related.) Set automatically in hardware when the as-
sertion of external interrupt 1 is detected. Cleared automatically when the proces-
sor calls the interrupt service routine.
2IT1
Interrupt Type 1 (Not timer-related.) Determines whether external interrupts are
strobed (edge-triggered) or held asserted (level-triggered). If ‘1’, external interrupt
1 is triggered by a falling signal edge. If ‘0’, it is triggered by a LOW input signal.
1IE0
Interrupt Edge 0 (Not timer-related.) Set automatically in hardware when the as-
sertion of external interrupt 0 is detected. Cleared automatically when the proces-
sor calls the interrupt service routine.
0IT0
Interrupt Type 0 (Not timer-related.) Determines whether external interrupts are
strobed (edge-triggered) or held asserted (level-triggered). If ‘1’, external interrupt
1 is triggered by a falling signal edge. If ‘0’, it is triggered by a LOW input signal.