User`s guide

LZ87010 Advance User’s Guide 8051-Compatible Timers
1/15/03 7-7
7.3.2 TMOD (Timer 0 and 1 Mode) Registers
Table 7-4. TMOD Register
BIT 7 6 5 4 3 2 1 0
FIELD GATE1 CN1 M1[1] M1[0] GATE0 CT0 M0[1] M0[0]
RESET 0 0 000000
RW RW RW RW RW RW RW RW RW
ADDR 0x89
Table 7-5. TMOD Register Bits
BIT NAME DESCRIPTION
7 GATE1
Timer 1 Gate Flag When this bit is ‘1’ Timer 1 runs only when the INT[1] pin is
HIGH. When this bit is ‘0’, Timer 1 runs continuously. (In either case, the timer
must be enabled in the TCON register.)
6CT1
Counter/Timer 1 Selector If ‘1’, Timer 1 is clocked by the CTIN1 pin (counter
operation). If ‘0’, Timer 1 is clocked internally by PCLK (timer operation).
5:4 M1[1:0] Mode Select Field See Table 7-6.
3 GATE0
Timer 0 Gate Flag When this bit is ‘1’ Timer 0 runs only when the INT[0] pin is
HIGH. When this bit is ‘0’, Timer 0 runs continuously. (In either case, the timer
must be enabled in the TCON register.)
2CT0
Counter/Timer 0 Selector If ‘1’, Timer 0 is clocked by the CTIN0 pin (counter
operation). If ‘0’, Timer 0 is clocked internally by PCLK (timer operation).
1:0 M0[1:0] Mode Select Field See Table 7-6.
Table 7-6. M(x)[1:0] Bit Field Decoding
M[1:0] DESCRIPTION
00
13-bit Timer/Counter Operation The TH(x) register holds the upper 8 bits of the count.
TL(x)[4:0] hold the lower five bits of the count. TL(x)[7:5] are undefined in this mode.
01
16-bit Timer/Counter Operation The TH(x) register holds the high byte of the count,
and the TL(x) register holds the low byte of the count.
10
8-bit Auto-reload Timer/Counter TL(x) holds the count. When the count overflows to
zero, TL(x) is reloaded with the value in TH(x).
11
Dual 8-bit Timer/Counter Operation
Timer 0: TL0 operates in either timer or counter mode, controlled by TMOD[3:2]. TH0
operates in timer mode only, controlled by TMOD[7:6].
Timer 1: This mode halts the timer.