User`s guide

1/15/03 8-1
Chapter 8
Enhanced Timers
The LZ87010 has four enhanced 16-bit timer/counters: Timer 2, Timer 3, Timer 4, and
Timer 5. These timers are not 8051-compatible. A top-level block diagram of these timers
is given in Figure 8-1.
All four timers are 16-bit count-up timers with the following features:
• Timing, where the counter free-runs and generates an interrupt when it overflows
• Counting, where the timer is incremented each time an external signal is asserted
• Compare, where each time the timer is incremented, it is compared to a specified value.
An interrupt or output pin is optionally asserted on a match.
• Capture (external event timing), where the current timer value is copied to a capture reg-
ister when an external capture signal is asserted, with an optional interrupt on capture.
(Timers 4 and 5 do not have the capture function.)
• Pulse-width Modulation (PWM), where two compare registers are used together to pro-
duce an output signal of any desired duty cycle.
The four timers are very similar to one another, but are not identical. Their differences are:
• Timer 2 and Timer 3 have the capture function, while Timer 4 and Timer 5 do not
• Timer 2 and Timer 4 have the ability to choose as their clock input the output of one of
the compare pins of Timer 3 and Timer 5, respectively
• Timer 2 and Timer 4 have a maximum clock divisor of 128. Timer 3 and Timer 5 have a
maximum clock divisor of 32,768.
The timers are otherwise identical.
Throughout this chapter, discussions applying to multiple timers will replace the timer
number with ‘(x)’. For example, the low-order timer count registers may be referred to as
‘T(x)CNTL’. In addition, the multiple capture and compare units per timer lead to the use
of, for example, the notation ‘T(x)CAP(y)L’ to indicate the low-order capture data in all the
capture units of each timer that has capture capability.