User`s guide

Enhanced Timers LZ87010 Advance User’s Guide
8-4 1/15/03
8.2.2 Writing 16-bit Timer Registers
Writes also have a mechanism to allow updating while the timer is running.This mechanism
also uses a temporary register and works the compare data register pairs (T(x)CMP0H and
T(x)CMP0L or T(x)CMP1H and T(x)CMP1L). Data is written first to the low-order register,
which the LZ87010 holds in a temporary register. When the high-order register is written,
the 16-bit target register pair is updated with the 16-bit quantity. See Figure 8-3.
For example:
// Write Timer 2 Compare 1 unit while Timer 2 is running.
// Correct order is always LSB first, then MSB.
MOV A,#EXAMPLE_LSB
MOV T2CMP1L,A // Write the LSB first,
MOV A,#EXAMPLE_MSB
MOV T2CMP1H,A // then the MSB.
Figure 8-2. Reading from Count and Capture Registers
TMP
8
T(x)CNTH
HIGH-BYTE DATA IS MOVED
TO A TEMPORARY REGISTER
WHEN LOW BYTE IS READ
HIGH-BYTE IS READ FROM
TEMPORARY REGISTER
T(x)CNTL
MOV reg, timer_data_low
T(x)CNTL
8
TMP
MOV reg, timer_data_high
T(x)CNTH
8
LZ87010-69
Figure 8-3. Writing to Compare Registers
TMP
8
T(x)CMP(y)L
LOW-BYTE DATA IS HELD
IN A TEMPORARY REGISTER
T(x)CMP(y)H
compare_data_low, data
8
TMP
8
T(x)CMP(y)L
BOTH BYTES ARE WRITTEN
WHEN THE HIGH BYTE IS WRITTEN
T(x)CMP(y)H
compare_data_high, data
LZ87010-70