User`s guide

LZ87010 Advance User’s Guide Enhanced Timers
1/15/03 8-5
8.2.3 Timer Clocking
Each timer has either three or four clock inputs, as shown in Figure 8-1. These always
include PCLK (the peripheral clock, which is always half the core clock), SUBCLK (the
32.768 kHz subclock), and an external clock input. Each timer has its own dedicated clock
input pin, CTIN2-CTIN5.
Timers 2 and 4 also have the option of using the output of an adjacent timer’s compare unit
output. Timer 2 can be clocked by TM3CMP1, and Timer 4 can be clocked by TM5CMP1.
This allows one timer to be used as a programmable clock generator for another timer.
Clock selection is controlled by the T(x)CON.CLK_SEL register field.
The maximum speed for external clocking on CTIN2-CTIN5 is two PCLK periods plus the
setup and hold times for the selected input.
Regardless of its source, the selected input clock is divided by a clock divider value. For
timers 2 and 4, the clock divider is one of: 1, 2, 4, 8, 16, 32, 64, 128. For timers 3 and 5, it
is one of: 1, 2, 4, 8, 16, 32, 64, 32,768. By using the 32.768 kHz subclock and a clock
divider of 32,768, one can achieve a one-second timer tick. The clock divider is selected
in the T(x)CON.DIV field.
8.2.4 Timing and Counting
A timer increments on each rising edge of the selected, divided clock. The count is kept in the
T(x)CNTH and T(x)CNTL registers. For example, the count of Timer 2 is kept in T2CNTH and
T2CNTL. T2CNTH holds the upper 8 bits of the count, while T2CNTL holds the lower 8 bits.
When the count overflows, the overflow bit in the timer’s status register (T(x)STA.OVF_ST)
will be set. This status bit will remain set until cleared by software. See Figure 8-4.
8.2.5 Capture
The input capture function is used to record the time at which external events occur. When
an external capture signal is asserted, the current timer value is copied into the corre-
sponding capture registers, a status bit is set, and an interrupt is optionally asserted.
Timers 2 and 3 have two capture input signals each: CTCAP2A, CTCAP2B, CTCAP3A,
and CTCAP3B. Timers 4 and 5 do not have capture inputs. See Table 8-2.
The capture signal is sampled on the rising edge of PCLK, and needs to be asserted for
at least one PCLK period plus the sample and hold times for the input. The capture can be
triggered on a rising edge, a falling edge, both, or neither. This is selected by the
T(x)CAP.IED[1:0] field.
Because the capture inputs can generate an interrupt on any selected signal edges, they
can be used as general-purpose edge-triggered interrupts.