User`s guide

Enhanced Timers LZ87010 Advance User’s Guide
8-8 1/15/03
8.2.6 Compare
All four enhanced timers have a dual compare function, where two 16-bit values can be
stored and compared against the current timer value. When a match occurs, an external
signal and an interrupt can be asserted. Both actions are optional and are independent of
one another.
The T(x)CMP(y).CMP0 and T(x)CMP(y).CMP1 bit fields determine the output polarity of
the compare unit. This is the polarity of the output on a compare match. The polarity of the
compare output is given in Table 8-4.
If the CMP(y) field is written with 0b01 or 0b10 (setting a HIGH on compare match or LOW
on compare match, respectively), its output is driven to the opposite of the polarity. When
a compare match occurs, the compare output is driven to the selected state for the duration
of the match—one timer clock cycle—then the output returns to the ‘no match’ state.
If the CMP(y) field is written with 0b00, the output is not changed, either before or after a
compare match.
If the CMP(y) field is written with 0b11, the output remains in its current state until a match
occurs. The compare output is then toggled on each compare match. The output is not
strobed for one timer cycle, but is held until the next compare match.
The output of the compare unit can be driven onto the CTCMP(x)(y) pins. Whether the
output pins are driven depends on bit-mapped output enables in the TCMPOE register.
Independently of whether an output
pin is driven, the compare output can be used as the
input clock for a waveform generator or (in the case of Timer 3 and Timer 5) the input clock
for another timer.
Writing to the GPIO ports that share the CTCMP(x)(y) pins has no effect on the compare
unit. In toggle mode, the compare unit inverts an internal state bit; it does not read the
GPIO bit.
The interrupt status of the compare unit is not affected by the output polarity or the state
of the TCMPOE enables. The status bit is set and, if enabled, an interrupt is asserted when
a timer match occurs. This interrupt is edge-triggered to ensure that multiple interrupts will
not happen with slow timer clocks.
The higher-numbered compare units (T(x)CMP1) can clear the counter on a compare
match. This is controlled by the T(x)CMP.TC bit.