User`s guide

LZ87010 Advance User’s Guide Enhanced Timers
1/15/03 8-11
8.2.7 PWM
In PWM mode, a timer’s two compare units are used together to form an output oscillator
with controllable frequency and duty cycle. Both compare units control the same pin,
CTCMP(x)A. The lower-numbered compare unit is programmed to drive the signal to one
state (LOW, for example) on a compare match, and the other compare unit is programmed
to drive the signal to the opposite state on a compare match, and to clear the counter. The
count starts again from zero, and the process repeats. PWM mode is enabled by setting
the T(x)CMP.PWM bit. See Figure 8-7. Output to the CTCMP(x)A pin must also be
enabled in the TCMPOE register.
To get the required duty cycle, set the 16-bit register pair of T(x)CMP0[H:L] to HIGH time
minus 1 (or LOW time minus 1, as desired) and the T(x)CMP1[H:L] registers to the period
minus 1.
For example, to get a 75% duty cycle, the PWM unit can be set to give 3 cycles of HIGH
time and 1 cycle of LOW time. This can be done by setting T(x)CMP1[H:L] = 3 (period
minus one), and T(x)CMP0[H:L] = 0 (LOW time minus one). See Figure 8-8. It can also be
achieved by setting T(x)CMP1[H:L] = 3 as before, but setting T(x)CMP0[H:L] = 2 (HIGH
time minus one) and inverting the polarity of the output in the T(x)CMP.CMP0 and
T(x)CMP.CMP1 fields.
Figure 8-7. PWM Operation
COUNT = T(x)CMP1
COUNT = T(x)CMP0
COUNT T(x)CNT[H:L]
T(x)CNT = 0
OUTPUT
CTCMP(x)A
NOTES:
1. Count (T(x)CNT) is incremented on every CLK cycle.
2. Count matches T(X)CMP0, set output = 1.
3. Count matches T(x)CMP1 set output = 0, clear counter.
TIME
LZ87010-93
See Note 3
See Note 1
See Note 2