User`s guide

LZ87010 Advance User’s Guide Enhanced Timers

1/15/03 8-17

8.3.3 T(x)CMP (Compare Control) Registers

Each timer has two compare units, T(x)CMP0 and T(x)CMP1, whose operating modes are

set in the T(x)CMP registers. The fields in these registers include interrupt enables, output

edge selects, and PWM mode select.

Table 8-17. T(x)CMP Registers

BIT 7 6 5 4 3 2 1 0

FIELD IOE1 IOE0 CMP1[1] CMP1[0] CMP0[1] CMP0[0] TC PWM

RESET 0000 0 000

RW RW RW RW RW RW RW RW RW

ADDR

T2CMP: 0xD3

T3CMP: 0xE3

T4CMP: 0xF3

T5CMP: 0xA3

Table 8-18. T(x)CMP Register Bits

BIT NAME DESCRIPTION

7IOE1

Interrupt Enable for Compare 1 If ‘1’, interrupts are generated on compare

complete. If ‘0’, no interrupt is generated.

6IOE0

Interrupt Enable, Compare 0 If ‘1’, interrupts are generated on compare

complete. If ‘0’, no interrupt is generated.

5:4 CMP1[1:0]

Compare Output Value Select 1 Sets the reference value (at which com-

pare match should occur) that is to be output to CTCMP(x)B when

T(x)CNT = T(x)CMP1.

00 = No change to CTCMP(x)B

01 = Output ‘0’ to CTCMP(x)B

10 = Output ‘1’ to CTCMP(x)B

11 = Toggle the output on each compare match

Each time this field is written with 0b01 or 0b10, the output state is set to the

opposite of the selected state to signal the ‘no match’ condition.

3:2 CMP0[1:0] Compare Output Value Select 0 As CMP1[1:0], but for Compare unit 0.

1TC

Timer Clear This bit selects between operation as a free running-counter or

as an interval counter. When ‘1’, the counter clears upon matching TxCMP1.

When ‘0’, the count continues after the match. This operation is only available

with the T(x)CMP1 registers.

0 = Inhibit counter clear (operates as free running counter)

1 = Clear counter upon T(x)CNT = T(x)CMP1

0PWM

Pulse Width Modulator This bit allows the use of CTCMP(x)A as a PWM

output. This is done by properly setting up this bit as well as other bits in this

in Compare mode.