User`s guide

LZ87010 Advance User’s Guide Enhanced Timers
1/15/03 8-19
8.3.5 T(x)CNTH and T(x)CNTL (Timer Count) Registers
The T(x)CNTH (timer count high) and T(x)CNTL (timer count low) registers contain the cur-
rent value of the 16-bit timers. These registers can be read at any time, but writes to these
registers while the timer is running will be ignored.
The timers are enabled and disabled in the T(x)CON (timer control) registers, which also
contain clock divider, interrupt enable, and other control fields. The T(x)CMP(y) (compare
control) registers contain a ‘clear on compare match’ field that, when enabled, will set the
timer count registers to zero whenever the count equals the compare value.
NOTE: Always read or write the LSB first, then the MSB. See Section 8.2.1 and Section 8.2.2.
Table 8-23. T(x)CNTH Register
BIT 7 6 5 4 3 2 1 0
FIELD CNT[15] CNT[14] CNT[13] CNT[12] CNT[11] CNT[10] CNT[9] CNT[8]
RESET 00000000
RW RW RW RW RW RW RW RW RW
ADDR
Timer 2: 0xDF
Timer 3: 0xEF
Timer 4: 0xFF
Timer 5: 0xAF
Table 8-24. T(x)CNTL Register
BIT 7 6 5 4 3 2 1 0
FIELD CNT[7] CNT[6] CNT[5] CNT[4] CNT[3] CNT[2] CNT[1] CNT[0]
RESET 0000 0 000
RW RW RW RW RW RW RW RW RW
ADDR
Timer 2: 0xDE
Timer 3: 0xEE
Timer 4: 0xFE
Timer 5: 0xAE