User`s guide

Watchdog Timer LZ87010 Advance User’s Guide
9-2 1/15/03
9.1.2 Stopping the Watchdog Timer in Idle Mode
If enabled, the Watchdog Timer continues to count in Idle mode, which is undesirable
unless the system is guaranteed to spend only a short period in Idle mode. During long
periods in Idle Mode, the Watchdog Timer might count down all the way to zero. If this hap-
pened, it would assert a Reset when Idle mode was exited. To prevent this, the Watchdog
Timer should be disabled before entering Idle mode, which will stop the counters. After Idle
mode is exited, the Watchdog Timer can be re-enabled.
9.2 Watchdog Timer Registers
9.2.1 WDTCTL Register
Table 9-1. WDTCTL Register
BIT 7 6 5 4 3 2 1 0
FIELD /// /// /// WDTPR[2] WDTPR[1] WDTPR[0] WDTEN WDTRL
RESET 00000000
RW RW RW RW RW RW RW RW W
ADDR 0xAC
Table 9-2. WDTCTL Register Bits
BIT NAME DESCRIPTION
7:5 /// Reserved Reads ‘0’, write ‘0’.
4:2 WDTPR[2:0]
Watchdog Timer Prescaler These bits determine the reload value of the
PRESCALE counter.
000b = PCLK ÷ 256
001b = PCLK ÷ 512
010b = PCLK ÷ 1,024
011b = PCLK ÷ 2,048
100b = PCLK ÷ 4,096
101b = PCLK ÷ 8,192
110b = PCLK ÷ 16,384
111b = PCLK ÷ 32,768
1WDTEN
Watchdog Timer Enable When set, the Watchdog Timer is enabled. When
clear, the Watchdog counters do not run and a reset will not be generated.
0 WDTRL
Watchdog Timer Reload Reads from this bit return zero. This is a write-
only bit. Writing a ‘0’ to this bit and then writing a ‘1’ within 32 CCLKs forces
a reload of the TIMEOUT counter. Otherwise, the writes have no effect. The
reload value is provided by the WDTCNT register. The reload operation is
not affected by the state of the WDTEN bit.