Service manual
GX30
6 – 21
CONFIDENTIAL
VideoDisplay IF
STKCHK
PalletRAM
RAM(B)
LCD
I/F
Reset
Halt
Ctrl
Clock
Generator
XIN/
SCANCK
XOUT
MasterClock (MCLK)
RD_B
WR_B
CS_B
Bus
Controller
Address
Generator
RGB
YUVIN0,2
RGBOUT0,2
32bit
32bit
BUF_
DATA0
BUF_
DATA1
BSPIXEL[7:0]
5~20MHzmax
BSCLK
BSHS_B
BS_CLK
BSBLK_B
6bit
6bit
6bit
Selector
LCD Output Timing Generator
LCD Panel Interface
DCLK
HSYNC
VSYNC
PWMLCD/PORT4
SE_DO/PORT0
SE_LD1/PORT2
SE_CK/PORT1
WAIT_B
RESET_B
Display Memory
320x240
Pixcel
(18bitx4
=72bit)
17 8bit
SUBDB[7:0]
SUBCKS
SUBCK
SUBRS
SUBCS_B
SUBWR_B
PLL
BSVS_B
HSEN
HSCK
CPU_DataBus
DB[7:0]
I/F
Timing
Control
4SCAN FRC
BUFOFF_B
FULL
Scan
TEST
TESTI
PWM/
PO
PWM0/PORT3
RAM(G)
Pallet
RAM(R)
8bitx256
17bit
MP4RESET_B
GTDIO_B
MP4_PLLCK
MP4_P0
RSP
Palette
I/F
Red Palette
Green Palette
Blue Palette
SUBFLMIN
SUBLPIN
Oscillation
ON/OFF
LCDTimingClock (TCLK)
5MHz~10MHz
LowSpeedClock (LCLK)
100 kHz~200 kHz
·····VRAM/HOST/HS/BS/
VDIF/VSPetc
·····TG/Pallet/LCD IF
/CDE/BS
·····SIO
MPEGClock (MPCLK)
15.36MHz or XIN
SCANCK
RDATA[5:0]
BDATA[5:0]
PLLDIV[2:0]
SCANEN
HSWRD
GDATA[5:0]
PO
LCDINT
SE_LD3/PORT6
SE_LD2/PORT5
PWMClock (PCLK)
XIN
clock
·····PWM
SUBLCDTimingClock
(STCK) XIN
clock
·····SUB
CameraClock (CAMCK)
CAMCK
HOST Interface
MaskBit Memory
320x240
Pixcel
(2bit)
Registor
DB[15:0]
ReadDATA
ReadDATA (72bit)
VDRD
SEL
HSD[7:0]
Read Buffer
Magnify
Magnification
circuit
Magnify
Magnification
circuit
Solidify
3D
circuit
Solidify
3D
circuit
SELSEL
SEL
72
WACK
WREQ
WriteDATA
RACK
RACK
PWM1/PORT8
R[4:0],B[4:0]
R[5:0]
B[5:0]
ColorDepthExpand
RED
Pallet
BLUE
Pallet
CDE
DCS_B
DA[1:0]
EXCS_B[3:0]
ADDRESS
DECODE
SE_DI/PORT7
Memory Interface
72bit BS_DATA[71:0]
SEL
Buffer
18bitx4
Buffer
18bitx4
Some MHz
to 68 MHz
PLL
Dividing
Oscillation
circuit
Current consumption
is decreased in a
standby mode.
Some MHz to 33 MHz
Approx.16.128 MHz
·····External MPEG4_ASIC
·····External
CAMERA_DSP
4-wire SO/PO
6bitx4
Available for
magnification
function
CPU system
buffer
MCLK system
buffer
Format conversion
circuit
Conversion from YUV
to RGB
(Available for high-
speed pipelines)
Pallet gamma circuit
RAM for mag/dif/sol
For error diffusion
LINE_Buffer (160 pixels x 36 x 1)
Buffer RAM for 1 line
For magnification function/
3D data sort function
LINE_Buffer (160 pixels x 48 x 4)
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
VideoSignalProcessor
Diffusion
Error diffusion
circuit
·18 bit x 4
·Vertical and horizontal
access
(No limitation for the
start address)
·Available for mask bit
Display size
320 x 240
Pixel
260,000
colors
RW
Command
function
(Trans-
mission)
RAM for BS mag/sol
For BS magnification function/
3D data sort function
LINE_Buffer (160 pixels x 48 x 4)
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
BS circuit
Available for
260,000 colors
Bit Stream circuit A
MCLK
phase
conversion
Buffer
control
creation
UV determination
and latch control
signal creation
H/V effective
signal creation
Buffer section
Available for
MPEG4
Commonly used
for sub-LCD
VRAM
Conversion
from YUV to RGB
PIO for
MPEG4ASIC
control
UV determination
and latch circuit
Conversion from
8-bit to 16-bit
External
clock
output
Available for sub-LCD
130,000 colors
Equivalent to LR38840