Specifications

36
Using BIOS
LDT Configuration (Enabled)
This item enables or disables the LDT configuration.
Upstream LDT Bus Width (16 bit)
This item allows users to manually adjust the upstream LDT bus width to be 8 bit or 16
bit.
Downstream LDT Bus Width (16 bit)
This item allows users to manually adjust the downstream LDT bus width to be 8 bit or
16 bit.
LDT Bus Frequency (Auto)
This item allows users to manually adjust the LDT Bus Frequency.
PCIE Reset Delay (Disabled)
This item enables or disables the PCIE reset delay.
Press <Esc> to return to the Advanced Chipset Features page.
Video RAM Cacheable (Enabled)
This item allows users to enable or disable the video ram cacheable function.
System BIOS Cacheable (Enabled)
This feature is only valid when the system BIOS is shadowed. It enables or disables the
caching of the system BIOS ROM at F0000h-FFFFFh via the L2 cache. This greatly
speeds up accesses to the system BIOS.
Integrated Peripherals
These options display items that define the operation of peripheral components on
the system’s input/output ports.
South OnChip IDE Device [Press Enter]
South OnChip PCI Device [Press Enter]
SuperIO Device [Press Enter]
Init Display First [PCI Slot]
Item Help
Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
Integrated Peripherals




F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help