Technical data

13773-001

91-10

Page 1

SYSTEM LOAD CHARTS AND BUS SCHEMATICS

1. GENERAL

The airplane is equipped with a two alternator system, with each alternator operating continuously. The for-

ward (ALT 1) alternator is a rated at 58 amps. The aft (ALT 2) alternator 2, is rated at 20 amperes. The total

system load of the airplane is supported by the two alternator configuration. The battery is charged in flight.

The total continuous connected load is held to less than 80% of the total rated generator output capacity.

During normal operation the system operates like two separate systems; ALT 1 provides power to battery 1

and the main distribution bus loads, and ALT 2 provides power to battery 2 and the essential distribution

bus loads. Low RPM operation or a failure of ALT 2 will cause all system loads and both batteries to be

bus continuous loads are held to less than 80% of the capacity of ALT 1 (80% of 58 A = 46.4 A).

Individual circuit loads have been determined by measuring the circuit loads as installed in the aircraft

using a calibrated ammeter. Loads stated for circuits with oscillating or varying power use are maximum

operating loads. These load measurements present the most accurate data for power usage available.

The airplane has seven power distribution busses with associated protection devices located within the

MCU:

Three busses are used as distribution feeders from the Main Distribution Bus.

Two busses are used as distribution feeders from the Essential Distribution Bus. All distribution feed-

ers are routed to the circuit breaker panel located near the pilot's right knee.

One bus is used to power the landing light directly from the Main Distribution Bus through a 15 amp cir-

cuit breaker.

One bus is the clock keep-alive bus, which is protected with a five amp fuse located in the side of the

MCU. The clock bus is the only bus not controlled by the master switch arrangement.

Figures 91-102 through 91-103 show current flow and the associated values at each bus for normal opera-

tion and during circuit failure. All current values are maximum device current draw including maximum

intermittent peaks, ensuring the essential bus will be powered during any combination of device use.

31 July 2001