User's Manual

ESP-32S User Manual
Shenzhen Ai-Thinker Technology Co., Ltd http://www.ai-thinker.com
Interface
Signal
Pin
Function
SPIHD
SHD/SD2
SPIWP
SWP/SD3
SPICS0
SCS/CMD
SPICLK
SCK/CLK
SPIQ
SDO/SD0
SPID
SDI/SD1
HSPICLK
IO14
HSPICS0
IO15
Supports Standard SPI, Dual SPI, and
Parallel QSPI
HSPIQ
IO12
Quad SPI that can be connected to the
HSPID
IO13
external flash and SRAM
HSPIHD
IO4
HSPIWP
IO2
VSPICLK
IO18
VSPICS0
IO5
VSPIQ
IO19
VSPID
IO23
VSPIHD
IO21
VSPIWP
IO22
HSPIQ_in/_out
Standard SPI consists of clock,
HSPID_in/_out
chip-select, MOSI and MISO. These SPIs
HSPICLK_in/_out
can be connected to LCD and other
HSPI_CS0_in/_out
external devices. They support the
HSPI_CS1_out
following features:
General Purpose
HSPI_CS2_out
Any GPIOs*
• both master and slave modes;
SPI
VSPIQ_in/_out
• 4 sub-modes of the SPI format
VSPID_in/_out
transfer that depend on the clock
VSPICLK_in/_out
phase (CPHA) and clock polarity
(CPOL) control;
• CLK frequencies by a divider;
• up to 64 bytes of FIFO and DMA.
VSPI_CS0_in/_out
VSPI_CS1_out
VSPI_CS2_out
MTDI
IO12
JTAG
MTCK
IO13
JTAG for software debugging
MTMS
IO14
MTDO
IO15