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DS-2472-01 <Rev.0.0> page 25/ 63
SPI Characteristics
Table 6. SPI Characteristics
SPI Time Diagrams
Figure 15 and 16 shows the timing diagram for 4-wire slave SPI and 3-wire slave SPI respectively. SPI master
will initiate a read or write operation by asserting SEN to low, toggling SCLK and sent the address field by SI.
The SEN should be high when a transaction is completed.
The SPI burst mode is provided for the access on a continuous basis. If SEN does not go high after the 8-bit
write data and the SCLK continuously toggles, the followed 8-bit write data is written to next address field.
Same for the read access, the data of the next address will be read.
Parameter Symbol Min Max Units Conditions
SCLK , clock frequency F
SCLK
5 MHz
SCLK low pulse duration t
CL
100 ns The minimum time SCLK must be low.
SCLK high pulse duration t
CH
100 ns The minimum time SCLK must be high.
SEN setup time t
SP
100 ns The minimum time SEN must be low before the first
positive edge of SCLK.
SEN hold time t
NS
100 ns The minimum time SEN must be held low after the last
negative edge of SCLK.
SI setup t
SD
25 ns
T
he minimum time data must be ready at SI, before th
e
positive edge of SCLK
SI hold time t
HD
25 ns The minimum time data must be held at SI, after the
positive edge of SCLK.
Rise time t
RISE
25 ns The maximum rise time for SCLK and SEN.
Fall time t
FALL
25 ns The maximum fall time for SCLK and SEN.