Product Info

DS-2472-01 <Rev.0.0>
page 31/ 63
4.6. RX
When a valid packet is received, an interrupt is issued at REG0x31[3]. The MCU host can read the whole packet
inside the RXFIFO. The RXFIFO is flushed when the frame length field and the last byte of RXFIFO are read, or
when the host triggers a RX flush by REG0x0D[0].
4.7. Power Saving
Standby, Deep-Sleep and Power-Down modes are designed for DKL 1908_V.1. It is only allowed to switch
between power saving modes and active mode. The following settings are effective in active mode only.
STANDBY Mode:
Shutdown RF/MAC/BB, while the voltage regulator, partial 16 MHz clock and sleep clock remains active.
 Set REG0x17[1:0] to ‘00’ to select for Standby mode
DEEP SLEEP Mode:
All power is shutdown except the power to the digital circuits and sleep clock. Register and FIFO are retained.
 Set REG0x17[1:0] to ‘01’ to select for Deep Sleep mode
POWER DOWN Mode:
All power is shutdown. Register and FIFO data are not retained. Initialization is needed after DKL 1908_V.1
back to active mode. Set REG0x17[1:0] to ‘11’ to select for Power Down mode
After the necessary settings mentioned above are configured, user can set REG0x35[7]=1 to place DKL
1908_V.1 to power saving mode. After set REG0x35[7]=1, the SEN Pin need to set to low (ground).
4.8. Wake-up
After entering into power saving mode, DKL 1908_V.1 could be waked up from STANDBY and DEEP_SLEEP
modes by simply setting REG0x22[6]=’1’. DKL 1908_V.1 will issue wake-up interrupt REG0x31[6] after
wakeup operation completion. For POWER_DOWN mode, DKL 1908_V.1 can be waked up by using external
reset pin (PIN11:RESETn).