Product Info

DS-2472-01 <Rev.0.0>
page 40/ 63
REG0x0D:
Bit 7 Reserved: Maintain as ‘0b000000’
Bit 1 DISTXW: Disable the function of TX trigger after register wakeup
1: Disable the function of TX trigger after register wakeup
0: Enable the function of TX trigger after register wakeup
Bit 0 RXFLUSH: Flush the RX FIFO
1: Flush RX FIFO. RX FIFO data is not modified. If Ping-pong FIFO is enabled (REG0x34[0]=1),
both FIFOs are flushed at the same time. Bit is automatically cleared to ‘0’ by hardware.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0
r r r r r r DISTXW RXFLUSH
R-0 R-0 R-0 R-0 R-0 R-0 R/W-0 WT-0