Product Info

DS-2472-01 <Rev.0.0>
page 50/ 63
REG0x1B:
Bit 7-4 TXRTYN: Maximum TX Retry Times
0000: 0
…
0011: 3 (default)
…
1111: 15
Bit 3 Reserved: Maintain as ‘0b0’
Bit 2 TXACKREQ: TX FIFO Acknowledgement Request bit
Transmit a packet with Acknowledgement request. If Acknowledgement is not received,
the DKL 1908_V.1 retransmits up to TXRTYN times.
0: (default) No Acknowledgement packet requested
1: Acknowledgement packet requested
Bit 1 Reserved: Maintain as ‘0b0’
Bit 0 TXTRIG: Transmit Frame in TX FIFO bit
1: Transmit the frame in the TX FIFO. Bit is automatically cleared to ‘0’ by hardware.
TRANSMIT FIFO CONTROL
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0
TXRTYN3 TXRTYN2 TXRTYN1 TXRTYN0 r TXACKREQ r TXTRIG
R/W-0 R/W-0 R/W-1 R/W-1 R-0 R/W-0 R-0 WT-0