Product Specs
Table Of Contents
- FEATURESAPPLICATIONS
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- PIN FUNCTIONS
- ELECTRICAL SPECIFICATIONS
- Package marking:
- Absolute Maximum Ratings
- Temperatures
- ATTENTION!
- Glossary of Terms
- FUNCTIONAL DESCRIPTION
- Pin functions in the different modes of nRF24L01
- Standby Modes
- Power Down Mode
- Packet Handling Methods
- ShockBurst™
- Enhanced ShockBurst™
- Enhanced ShockBurst™ Transmitting Payload:
- Enhanced ShockBurstTM Receive Payload:
- DEVICE CONFIGURATION
- SPI Interface
- SPI Instruction Set
- Interrupt
- SPI Timing
- Memory Map
- Configuration for compatibility with nRF24XX
- PACKET DESCRIPTION
- IMPORTANT TIMING DATA
- nRF24L01 Timing Information
- Enhanced ShockBurst™ timing
- PERIPHERAL RF INFORMATION
- Output Power adjustment
- Crystal Specification
- nRF24L01 sharing crystal with a micro controller.
- Crystal parameters:
- Input crystal amplitude & Current consumption
- PCB layout and de-coupling guidelines
- APPLICATION EXAMPLE
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
- YOUR NOTES
- 空白页面
- 空白页面
- 空白页面
- 空白页面
PRELIMINARY PRODUCT SPECIFICATION
nRF24L01 Single Chip 2.4 GHz Radio Transceiver
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Page 23 of 38
Revision: 1.1
November 2005
Address
(Hex)
Mnemonic
Bit
Reset
Value
Type
Description
Available locations in TX FIFO.
08
OBSERVE_TX
Transmit observe register
PLOS_CNT
7:4
0
R
Packet Loss Counter. The register is reset
by writing to RF_CH. The counter
restarts after 15 lost packets. See page 14
and 16.
ARC_CNT
3:0
0
R
Current value on resent counter. The
counter is reset when transmission of a
new packet starts. See page 14.
09
CD
Reserved
7:1
000000
R
CD
0
0
R
Carrier Detect. See page 16.
0A
RX_ADDR_P0
39:0
0xE7E7E7E7E7
R/W
Receive address data pipe 0. 5 Bytes
maximum length. (LSByte is written first)
0B
RX_ADDR_P1
39:0
0xC2C2C2C2C2
R/W
Receive address data pipe 1. 5 Bytes
maximum length. (LSByte is written first)
0C
RX_ADDR_P2
7:0
0xC3
R/W
Receive address data pipe 2. Only LSB.
MSBytes will be equal to
RX_ADDR_P1[39:8]
0D
RX_ADDR_P3
7:0
0xC4
R/W
Receive address data pipe 3. Only LSB.
MSBytes will be equal to
RX_ADDR_P1[39:8]
0E
RX_ADDR_P4
7:0
0xC5
R/W
Receive address data pipe 4. Only LSB.
MSBytes will be equal to
RX_ADDR_P1[39:8]
0F
RX_ADDR_P5
7:0
0xC6
R/W
Receive address data pipe 5. Only LSB.
MSBytes will be equal to
RX_ADDR_P1[39:8]
10
TX_ADDR
39:0
0xE7E7E7E7E7
R/W
Transmit address. Used for a PTX device
only. (LSByte is written first)
Set RX_ADDR_P0 equal to this address
to handle automatic acknowledge if this is
a PTX device with Enhanced
ShockBurst™ enabled. See page 14.
11
RX_PW_P0
Reserved
7:6
00
R/W
Only '00' allowed
RX_PW_P0
5:0
0
R/W
Number of bytes in RX payload in data
pipe 0 (1 to 32 bytes).
0 Not Legal
1 = 1 byte
…
32 = 32 bytes
12
RX_PW_P1
Reserved
7:6
00
R/W
Only '00' allowed
RX_PW_P1
5:0
0
R/W
Number of bytes in RX payload in data
pipe 1 (1 to 32 bytes).
0 Not Legal
1 = 1 byte
…
32 = 32 bytes
13
RX_PW_P2
Reserved
7:6
00
R/W
Only '00' allowed
RX_PW_P2
5:0
0
R/W
Number of bytes in RX payload in data
pipe 2 (1 to 32 bytes).