Specifications

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Preface, Contents

CPUs

CPU 31x-2 as DP Master/DP

Slave and Direct Communication

Cycle and Reaction times

CPU Function, depending on

CPU and STEP 7 Version

Tips and Tricks

Appendix

Standards, Certificates and

Approvals

Dimensioned Drawings

List of Abbreviations

Glossary, Index

Edition 10/2001

A5E00111190-01

PLC S7-300,

CPU Specifications CPU 312 IFM

to CPU 318-2 DP

Reference Manual

SIMATIC

This manual is part of the documentation

package with the order number

6ES7398-8FA10-8BA0

This documentation can no longer be ordered under

the given number!

Summary of content (190 pages)

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Preface, Contents SIMATIC PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP Reference Manual CPUs 1 CPU 31x-2 as DP Master/DP Slave and Direct Communication 2 Cycle and Reaction times 3 CPU Function, depending on CPU and STEP 7 Version 4 Tips and Tricks 5 Appendix Standards, Certificates and Approvals A Dimensioned Drawings B List of Abbreviations C Glossary, Index This documentation can no longer be ordered under the given number! This manual is part of the documentation packag
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Safety Guidelines This manual contains notices intended to ensure personal safety, as well as to protect the products and connected equipment against damage. These notices are highlighted by the symbols shown below and graded according to severity by the following texts: ! ! ! Danger indicates that death, severe personal injury or substantial property damage will result if proper precautions are not taken.
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Preface Purpose of the Manual This manual gives you a brief overview of 312 IFM to 318-2 CPUS in an S7-300. You can look up information on how to operate the system, its functions and technical data of the CPUs. Essential know-how General knowledge of automation technology is required for comprehension of this Manual. You should also be acquainted with basic STEP 7 software as described in your Programming with STEP 7 V 5.1 Manual.
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Preface Scope of the Manual The manual covers the following CPUs and Hardware/Software versions: CPU CPU 312 IFM As of Version Order No. 6ES7 312-5AC02-0AB0 Firmware Hardware 1.1.0 01 6ES7 312-5AC82-0AB0 CPU 313 6ES7 313-1AD03-0AB0 1.1.0 01 CPU 314 6ES7 314-1AE04-0AB0 1.1.0 01 6ES7 314-1AE84-0AB0 CPU 314 IFM 6ES7 314-5AE03-0AB0 6ES7 314-5AE83-0AB0 1.1.0 01 CPU 314 IFM 6ES7 314-5AE10-0AB0 1.1.0 01 CPU 315 6ES7 315-1AF03-0AB0 1.1.
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Preface Approbation, Standards and Approvals The SIMATIC S7-300 series conforms to: Requirements and criteria to IEC 61131, Part 2 CE labeling – EC Guideline 73/23/EEC on Low Voltages – EC Guideline 89/336/EEC on electromagnetic compatibility (EMC) Canadian Standards Association: CSA C22.2 Number 142, tested (Process Control Equipment) Underwriters Laboratories, Inc.: UL 508 registered (Industrial Control Equipment) Underwriters Laboratories, Inc.
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Preface Integration in the Information Technology Environment This Manual forms part of the S7-300 documentation package: You are reading this manual Reference Manual “CPU Data” CPU Data of CPU 312 IFM to 318-2 DP Description on how to operate, of the functions and of technical data of the CPU CPU Data of CPU 312C to 314C-2 PtP/DP “Technological Functions” Manual Manual Description of specific technological functions: Samples Positioning Counting Point-to-point connection Rules The CD con
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Preface Complementary to this documentation package you require the following manuals: Manual “Integrated Functions CPU 312 IFM/314 IFM” Description of technological functions of the CPUs 312 IFM/314 IFM. Manual Order no.: 6ES7398-8CA00-8BA0 Reference Manual “System Software for S7-300/400 System and Standard Functions” Reference manual Part of the STEP 7 documentation package, order no. 6ES7810-4CA05-8BR0 Figure 1-2 Description of the SFCs, SFBs and OBs of the CPUs.
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Preface Automation and Drives, Service & Support World-wide available 24-hours: Nuremberg Johnson City Singapore SIMATIC Hotline World-wide (Nuremberg) World-wide (Nuremberg) Technical Support Technical Support (Free Contact) (charged, only with SIMATIC Card) Local time: Mo.-Fr. 0:00 AM to 24:00 PM Local time: AM to 17:00 PM Mo.-Fr. 7:00 +49 (180) 5050-222 Phone: +49 (911) 895-7777 Fax: +49 (180) 5050-223 Fax: +49 (911) 895-7001 E-mail: techsupport@ ad.siemens.
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Preface SIMATIC Documentation on the Internet Documentation is available free of charge on the Internet under: http://www.ad.siemens.de/support Please use the Knowledge Manager offered at these locations for quick location of your required documentation. Our Internet Forum offers a “Documentation” conferencing room for your questions and solution proposals. http://www.ad.siemens.
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Preface x PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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Contents 1 2 CPUs 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 Control and Display Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status and Fault Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Selector Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Backup battery/accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory card . . . . . . . . .
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Contents 3 4 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 2.6.8 2.6.9 2.6.10 Diagnosis of the CPU 31x-2 operating as DP-Slave . . . . . . . . . . . . . . . . . . Diagnosis with LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostics with STEP 5 or STEP 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading Out the Diagnostic Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format of the Slave Diagnostic Data . .
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Contents Figures 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 3-1 3-2 3-3 3-4 4-1 B-1 B-2 B-3 B-4 B-5 Control and Display Elements of the CPUs . . . . . . . . . . . . . . . . . . . . . . . . . Status and Fault Displays of the CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Principle of Connection Resource Allocation for CPU 318-2 . . . . . . . . . . . The Principle of Forcing with S7-300 CPUs (CPU 312IFM to 316-2DP) .
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Contents Tables 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 xiv The Differences in Control and Display Elements Between CPUs . . . . . . Using a Backup Battery or Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Interfaces . . . . . . . . . . . . . . . . . . .
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1 CPUs In This Section Section Contents Page 1.1 Control and Display Elements 1-2 1.2 CPU Communication Options 1-11 1.3 Test Functions and Diagnostics 1-19 1.
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CPUs 1.1 Control and Display Elements Figure 1-1 shows you the control and display elements of a CPU. The order of the elements in some CPUs might differ from the order shown in the figure below. The individual CPUs do not always have all the elements shown here. Table 1-1 shows you the differences.
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CPUs 1.1.1 Status and Fault Displays Displays for the CPU: SF ... (red) ...hardware/software error BATF ... (red) ...battery error (not CPU 312 IFM) DC5V ... (green) ... 5V DC supply for CPU and S7-300 bus is ok. FRCE ... (yellow) ...force job is active RUN ... (green) ... CPU in RUN mode; LED flashes at start-up with 1 Hz; in HALT mode with 0.5 Hz STOP ... (yellow) ... CPU in STOP/HALT or STARTUP mode; LED flashes on request to reset memory Displays for the PROFIBUS: CPU 315-2 DP/ CPU 316-2 DP BUSF ...
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CPUs 1.1.2 Mode Selector Switch The mode selector is the same in all CPUs. Mode Selector Positions The positions of the mode selector are explained in the order in which they appear on the CPU. Details on CPU operating modes are found in the STEP 7 Online Help . Position Description RUN-P RUN-PROGRAM mode RUN mode RUN mode Description The CPU scans the user program. The key cannot be taken out in this position. The CPU scans the user program.
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CPUs 1.1.3 Backup battery/accumulator Exceptions The CPUs 312IFM and 313 do not have a real time clock so they do not need an accumulator battery. The CPU 312IFM does not have a buffer which means that you can not insert a battery. Backup battery or rechargeable battery? Table 1-2 shows the differences in the backup provided by an accumulator and a backup battery. Table 1-2 Backup with... Using a Backup Battery or Accumulator ...
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CPUs 1.1.4 Memory card Exceptions You cannot insert a memory card with the CPUs 312 IFM and 314 IFM (-5AE0x). These CPUs have an integrated read-only memory. Purpose of the Memory Card With the memory card, you can expand the load memory of your CPU. You can store the user program and the parameters that set the responses of the CPU and modules on the memory card. You can also back up your CPU operating system to a Memory Card. except CPU 318-2.
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CPUs 1.1.5 MPI and PROFIBUS-DP Interface Table 1-4 CPU Interfaces CPU 315-2DP CPU 316-2DP CPU 312 IFM CPU 313 CPU 314IFM CPU 314 MPI interface MPI interface MPI PROFIBUS-DP interface MPI - - CPU 318-2 MPI/DP Interface MPI/ DP DP - PROFIBUS-DP interface Reconfiguration as a PROFIBUS-DP interface is possible DP - MPI interface The MPI is the interface of the CPU for the programming device/OP and for communication in an MPI subnet. Typical (default) transmission speed is 187.
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CPUs Connectable Devices MPI PROFIBUS-DP Programming device/PC and OP S7 programmable controller with MPI interface (S7-300, M7-300, S7-400, M7-400, C7-6xx) Programming device/PC and OP S7 programmable controllers with the PROFIBUS-DP interface (S7-200, S7-300, M7-300, S7-400, M7-400, C7-6xx) S7-200 (Note: 19.2 Kbps only) Other DP masters and DP slaves Only 19.2 Kbps for S7-200 in MPI Subnet Note At 19.
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CPUs Loss of GD packets Following Change in the MPI Subnet During Operation ! Warning Loss of data packets in the MPI subnet: Connecting an additional CPU to the MPI subnet during operation can lead to loss of GD packets and to an increase in cycle time. Remedy: 1. Disconnect the node to be connected from the supply. 2. Connect the node to the MPI subnet. 3. Switch the node on.
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CPUs 1.1.6 Clock and Runtime Meter Table 1-5 shows the characteristics and functions of the clock for the various CPUs. When you assign parameters to the CPU in STEP 7, you can also set functions such as synchronization and the correction factor(see the STEP 7 online help system).
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CPUs Behavior of Clock in POWER OFF Mode The following table shows the clock behavior with the power of the CPU off, depending on the backup: Backup With backup battery CPU 314 to 318-2 The clock continues to operate in power off mode. With The clock continues to operate in accumulator power off mode for the backup time of the accumulator. When the power is on, the accumulator is recharged.
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CPUs Table 1-6 CPU Communication Options MPI DP PG/OP Communication x x A CPU can maintain several on-line connections simultaneously with one or more programming devices or operator panels. For PD/OP communication via the DP interface, you must activate the “Programming, modifying and monitoring via the PROFIBUS” function when configuring and assigning parameters to the CPU.
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CPUs Connection Resources Every communication connection requires a communication resource on the S7 CPU as a management unit for the duration of the communication. Every S7 CPU has a certain number of connection resources available to it according to its technical specifications which can be assigned to various communication services (PD/OP communication, S7 communication or S7 basic communication).
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CPUs Connection Resources for CPUs 312IFM to 316-2 DP Communication resources are independent of the interface in CPUs 315-2 DP and 316-2 DP. That is, a PG communication occupies a connection resource, regardless of whether the connection was established via MPI or DP interface.
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CPUs Connection Resources for CPU 318-2 Table 1-8 Communication Resources for CPU 318-2 Description Communication Function PD/OP communication S7 basic communication The CPU 318-2 provides a total of 32 connection resources (with CPU as connection terminal point) for these communication functions. Those 32 connection resources can be freely allocated to the various communication functions.
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CPUs Interface Resources for CPU 318-2 - Example Calculation 1. Two network transitions by routing on the CPU Resources used: - 2 connection resources of the MPI/DP interface are used; - 2 connection resources of the DP interface are used; - all 4 connection resources available to both interfaces are used; 2.
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CPUs CPU 312 IFM to 316-2 DP CPU 318-2 PUT/GET functions of S7 communication, or reading/writing variables via OP communication, are processed during the cycle checkpoint of the CPU. PUT/GET functions of S7 communication, or reading/writing to variable via OP communication are processed in defined time windows in the CPU 318-2 operating system.
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CPUs Details ... on the communication topic are found in the STEP 7 Online Help and in the manual Communication with SIMATIC. ... on communications SFCs/SFBs are found in the STEP 7 Online Help and in the Standard and System functions reference manual. Global Data Communication with S7-300 CPUs Below you will find important features of global data communication in the S7-300.
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CPUs 1.3 Test Functions and Diagnostics The CPUs provide you with: 1.3.1 Testing functions for commissioning Diagnostics via LEDs and STEP 7. Testing Functions The CPUs offer you the following testing functions: Monitor Variables Modify Variables Forcing (note the differences between CPUs) Monitor block Set Breakpoint Details on the testing functions are found in the STEP 7 Online Help.
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CPUs Different Features of Forcing S7-300 Please note the different features of forcing in the different CPUs: CPU 312IFM to 316-2DP CPU 318-2 1-20 The variables of a user program with fixed preset values (force values) cannot be changed or overwritten by the user program. It is not permissible to force peripheral or process image areas lying in the range of consistent user data. The variables of a user program with fixed preset values (force values) can be changed or overwritten in the user program.
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CPUs Forcing with the CPU 312 IFM to 316-2 DP: ! Caution Forced values in the input process image can be overwritten by write instructions (e.g. T EB x, = E x.y, copying with SFC etc.) and peripheral read instructions (e.g. L PEW x) in the user program, as well as by write instructions of PG/OP operations! Outputs initialized with forced values only return the forced value if the user program does not execute any write accesses to the outputs using peripheral write commands (e.g.
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CPUs 1.3.2 Diagnostics with LED Display In Table 1-9, only the LEDs relevant to the diagnosis of the CPU and S7-300 are listed. You will find the significance of the PROFIBUS-DP interface LEDs explained in Chapter 2.
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CPUs CPU Reaction on Missing Error OB If you have not programmed an error OB, the CPU reacts as follows: CPU goes into STOP on missing ... OB 80 (Runtime error) OB 85 (Program cycle error) OB 86 (Station failure in the PROFIBUSDP subnet) OB 87 (Communication error) OB 121 (Programming error) OB 122 (Peripheral direct access error) CPU Remains in RUN with Missing ...
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CPUs 1.4 CPUs - Technical Specifications In This Section You will find the technical specifications of the CPU. You will find the technical specifications of the integrated inputs/outputs of the CPU 312 IFM and 314 IFM. You will not find the features of the CPU 31x-2 DP as a DP master/DP slave. Refer to Chapter 2. Section 1-24 Contents Page 1.4.1 CPU 312 IFM 1-25 1.4.2 CPU 313 1-37 1.4.3 CPU 314 1-40 1.4.4 CPU 314 IFM 1-43 1.4.5 CPU 315 1-60 1.4.6 CPU 315-2 DP 1-63 1.4.
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CPUs 1.4.1 CPU 312 IFM Special Features Integrated I/Os (Wiring via 20-pole front connector) No backup battery and therefore maintenance-free An S7-300 with CPU 312 IFM can be mounted only on one rack Integrated Functions of the CPU 312 IFM Integrated Functions Process interrupt Description Interrupt input means: inputs configured with this function trigger a process interrupt at the corresponding signal edge. Interrupt input options for the digital inputs 124.6 to 125.
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CPUs Start information for OB40 Table 1-10 shows the temporary (TEMP) variables of OB40 relevant for the “Interrupt inputs” of the CPU 312 IFM. Refer to theSystem and Standard functions reference manual for details on the process interrupt OB.
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CPUs Front View Status and fault LEDs Mode selector Multipoint Interface (MPI) I124.0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I125.0 I 1 Q124.0 Q 1 Q 2 Q 3 Q 4 Q 5 Front connector, used to connect the integrated I/O, power supply and system ground.
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CPUs Technical Specifications of the CPU 312 IFM CPU and Product Version MLFB Data areas and their retentive characteristics 6ES7 312-5AC02-0AB0 Hardware version 01 Firmware version V 1.1.0 Matching programming package STEP 7 V 5.0; Service Pack 03 Retentive data area as a whole (inc. flags, timers, counters) max. 1 DB, 72 data bytes Bit memories 1024 Memory Work memory Clock memories 8 (1 memory byte) Data blocks max.
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CPUs Configuration Communication functions Rack 1 PD/OP communication Yes Modules per module rack max. 8 Global data communication Yes DP Master Number of GD packets integral None – Sender 1 via CP Yes – Receiver 1 S7 message functions Simultaneously active None Size of GD packets max. 22 bytes – 8 bytes Alarm-S blocks Time Real-time clock Yes Backed-up No Accuracy See Section 1.1.
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CPUs MPI Voltages, Currents Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server) Transmission rates 19.2; 187.5 Kbps Dimensions Assembly dimension B H T (mm) 80 125 130 Weight Approx. 0.45 kg Power supply 24V DC 20.4 to 28.8 V Permissible range Current consumption (idle) typical 0.7 A Inrush current typical 8A l2t 0.
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CPUs Technical Specifications of the Special Inputs of the CPU 312IFM Module-Specific Data Number of inputs Sensor Selection Data 4 I 124.6 to 125.1 Cable length Shielded Input voltage Rated value For “1” signal I 125.0 and I 125.1 I 124.6 and I 124.7 max. 100 m (109yd.) Voltages, Currents, Potentials For “0” signal Number of inputs that can be triggered simultaneously Input current 4 15 to 30 V 15 to 30 V -3 to 5 V For “1” signal (horizontal configuration) 24V DC I 125.
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CPUs Technical Specifications of the Digital Inputs of the CPU 312IFM Note Alternatively, you can configure the inputs I 124.6 and I 124.7 as special inputs, in which case the technical specifications listed for the special inputs apply to the inputs I 124.6 and I 124.7. Module-Specific Data Number of inputs Status, Interrupts; Diagnostics 8 Status display 1 green LED per channel max. 600 m Interrupts None max.
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CPUs Technical Specifications of the Digital Outputs of the CPU 312IFM Module-Specific Data Number of outputs Actuator Selection Data 6 For “1” signal Cable length Unshielded Shielded Output voltage max. 600 m Output current max. 1000 m For “1” signal Voltages, Currents, Potentials Total current of outputs (per group) min. L+ (-0.8 V) Rated value 0.5 A Permissible range 5 mA to 0.6 A For “0” signal (horizontal Residual current max. 0.5 mA configuration) max.
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CPUs Wiring diagram of the CPU 312 IFM Figure 1-7 shows the wiring diagram of the CPU 312 IFM. Use a 20-pole front connector to wire the CPU’s integrated I/O. ! Caution The CPU 312 IFM has no reverse polarity protection. Polarity reversal destroys the integrated outputs. Nonetheless, in this case the CPU does not switch to STOP and the status displays are lit. In other words, the fault is not indicated. I124.0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I125.0 I 1 Q124.
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CPUs Power Supply Connections The CPU 312 IFM and the integrated I/Os are connected to power at the terminals 18 and 19 (see Figure 1-7). Short-circuit reaction On short-circuit at one of the integrated outputs of CPU 312 IFM, proceed as follows: 1. Switch the CPU 312 IFM to STOP or switch off the power supply. 2. Eliminate the cause of the short-circuit. 3. Switch the CPU 312 IFM back to RUN or switch the power supply back on.
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CPUs Basic Circuit Diagram of the CPU 312 IFM Figure 1-8 shows the block diagram of CPU 312 IFM.
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CPUs 1.4.2 CPU 313 Technical Specifications of the CPU 313 CPU and Product Version MLFB Data areas and their retentive characteristics 6ES7 313-1AD03-0AB0 Hardware version 01 Firmware version V 1.1.0 Matching programming package STEP 7 V 5.0; Service Pack 03 Retentive data area as a whole (inc. flags, timers, counters) max. 1 DB, 72 data bytes Bit memories 2048 Memory Work memory Clock memories 8 (1 memory byte) Data blocks max.
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CPUs Configuration Communication functions Rack 1 PD/OP communication Yes Modules per module rack max. 8 Global data communication Yes Number of DP masters Number of GD packets integral No – Sender 1 via CP 1 – Receiver 1 S7 message functions Simultaneously active None Size of GD packets max. 22 bytes – 8 bytes Alarm-S blocks Time Real-time clock Backed-up No Accuracy See Section 1.1.6 Operating hours counter User data per job max.
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CPUs MPI Voltages, Currents Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server) Transmission rates 19.2; 187.5 Kbps Dimensions Power supply 24V DC Permissible range 20.4 to 28.8 Current consumption (idle) typical 0.7 A Inrush current typical 8A l2t 0.4 A2s External fusing for supply lines (recommendation) Circuit breaker; 2 A PD supply at MPI (15 to 30V DC) max.
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CPUs 1.4.3 CPU 314 Technical Specifications of the CPU 314 CPU and Product Version MLFB Data areas and their retentive characteristics 6ES7 314-1AE04-0AB0 Hardware version 01 Firmware version V 1.1.0 Matching programming package STEP 7 V 5.0; Service Pack 03 Retentive data area as a whole (inc. flags, timers, counters) 4736 bytes Bit memories 2048 Memory Work memory Clock memories 8 (1 memory byte) Data blocks max.
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CPUs Configuration Communication functions Rack max. 4 PD/OP communication Yes Modules per module rack max. 8 Global data communication Yes Number of DP masters Number of GD packets integral None – Sender 1 via CP 1 – Receiver 1 S7 message functions Simultaneously active max. 40 Size of GD packets max. 22 bytes – 8 bytes Alarm-S blocks Time Real-time clock Backed-up Yes Accuracy See Section 1.1.6 Operating hours counter User data per job max.
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CPUs MPI Voltages, Currents Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server) Transmission rates 19.2; 187.5 Kbps Dimensions Power supply 24V DC 20.4 V to 28.8 V Permissible range Current consumption (idle) typical 0.7 A Inrush current typical 8A l2t 0.4 A2s External fusing for supply lines (recommendation) Circuit breaker; 2 A, PD supply at MPI (15 to 30V DC) max.
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CPUs 1.4.4 CPU 314IFM Special Features Integrated I/Os (wired with 40-pole front connector) Details on analog value processing and how to connect measuring transducers, load and actuators to analog I/O is found in the Module Data reference manual. Figures 1-14 and 1-15 on page 1-59 show wiring examples. Memory card The CPU 314 IFM is available in 2 versions: with and without Memory Card slot.
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CPUs “Interrupt Inputs” of the CPU 314 IFM If you want to assign interrupt functions to the digital inputs 126.0 to 126.4, configure your CPU parameters in STEP 7 accordingly. Note the following points: These digital inputs have a very low signal delay. At this interrupt input, the module recognizes pulses with a length as of approx. 10 to 50 s. Always use shielded cable to connect active interrupt inputs in order to avoid interrupts triggered by line interference.
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CPUs Display of the Interrupt Inputs In variable OB40_POINT_ADDR, you can view the interrupt inputs which have triggered a process interrupt. Figure 1-9 shows the allocation of the interrupt inputs to the bits of the double word. Note: Several bits can be set if interrupts are triggered by several inputs within short intervals (< 100 s). That is, the OB is started once only, even if several interrupts are pending. 5 4 3 2 1 0 31 30 Bit No. Reserved PRIN from PRIN from PRIN from PRIN from I126.0 I126.
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CPUs Front View of the CPU 314 IFM OUT IN OUT M L + M Status and error LEDs Mode selector switch Compartment for backup battery or rechargeable battery Jumper (removable) Connection for power supply and system ground Multipoint interface MPI Integrated I/Os Memory Card slot (only -5AE10-) Figure 1-10 Front View of the CPU 314 IFM 1-46 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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CPUs Technical Specifications of the CPU 314 IFM CPU and Product Version MLFB 6ES7 314-...-0AB0 Data areas and their retentive characteristics -5AE03- -5AE10- Hardware version 01 01 Firmware version V 1.1.0 V 1.1.0 Matching programming package STEP 7 V5.0, Service Pack 3 Retentive data area as a whole (inc. flags, timers, counters) max. 2 DB, 144 bytes Bit memories 2048 Memory Work memory Clock memories 8 (1 memory byte) Data blocks max.
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CPUs Configuration Communication functions Rack max. 4 PD/OP communication Yes Modules per module rack max. 8; max. 7 in module rack 3 Global data communication Yes Number of DP masters integral None via CP 1 S7 message functions Simultaneously active Time Yes Accuracy See Section 1.1.6 1 1 Size of GD packets max. 22 bytes – 8 bytes Number of which consistent Yes User data per job max.
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CPUs MPI Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server) Transmission rates 19.2; 187.5 Kbps Dimensions Assembly dimension B H T (mm) 160 125 130 Weight Approx. 0.9 kg PD supply at MPI (15 to 30V DC) max. 200 mA Power losses Typically 16 W Battery Yes Backup margin at 25 C and continuous CPU buffering min. 1 year Battery shelf life at 25 C approx.
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CPUs Characteristic Features of the Integrated Inputs and Outputs of the CPU 314 IFM Table 1-12 Characteristic Features of the Integrated Inputs and Outputs of the CPU 314 IFM Characteristics Inputs/Outputs Analog inputs Analog output Digital inputs Digital outputs 1-50 Voltage inputs 10 V All information required for Current inputs 20 mA analog value display, as well as Resolution 11 bits + sign bit Galvanically isolated Voltage output 10 V Current output 20 mA Resolut
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CPUs Technical Specifications of the Analog Inputs of the CPU 314IFM Module-Specific Data Number of inputs 4 Cable length Shielded max. 100 m (109yd.) Voltages, Currents, Potentials Galvanic isolation between channels and between inputs and MANA (UCM) between MANA and Conversion time/Resolution (per channel) Basic conversion time Resolution (inc. overdrive range) Common-mode Linearity error (referred to input range) 0.
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CPUs Technical Specifications of the Analog Output of the CPU 314IFM Module-Specific Data Number of outputs Output ripple; Range of 0 to 50 kHz (referring to output range) 1 Cable length Shielded 0.05 % Status, Interrupts; Diagnostics max. 100 m (109yd.
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CPUs Technical Specifications of the Special Inputs of the CPU 314IFM Module-Specific Data Number of inputs Sensor Selection Data 4 I 126.0 to 126.3 Cable length Shielded Input voltage Rated value For “1” signal max. 100 m (109yd.
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CPUs Technical Specifications of the Digital Inputs of the CPU 314IFM Module-Specific Data Number of inputs Status, Interrupts; Diagnostics 16 Status display 1 green LED per channel max. 600 m Interrupts None max.
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CPUs Technical Specifications of the Digital Outputs of the CPU 314IFM Remarks When the supply voltage is switched on a pulse occurs on the digital outputs! This can be 50 ms long within the permissible output current range. You must not, therefore, use the digital outputs to trigger high-speed counters. Module-Specific Data Number of outputs Actuator Selection Data 16 For “1” signal Cable length Unshielded Shielded Output voltage max. 600 m Output current max.
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CPUs Wiring diagram of the CPU 314 IFM Figure 1-11 shows the wiring diagram of the CPU 314 IFM. For the connection of integrated I/O you require two 40-pole front connectors (Order no.: 6ES7392-1AM00-0AA0). Always wire up digital inputs 126.0 to 126.3 with shielded cable due to their low input delay time. ! Caution Wiring errors at the analog outputs can cause the integrated analog I/O of the CPU to be destroyed! (for example, if the interrupt inputs are wired by mistake to the analog output).
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CPUs Basic Circuit Diagrams of the CPU 314 IFM Figures 1-12 and 1-13 show the basic circuit diagrams for the integrated inputs/outputs of the CPU 314 IFM.
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CPUs 1 L+ 2L+ 24V M M CPU interface 2M 3L+ 24V 1M M 3M 24V Figure 1-13 Basic Circuit Diagram of the CPU 314 IFM (Digital Inputs/Outputs) 1-58 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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CPUs Wiring the Analog Inputs 1 L+ AIU AII AI_ L+ 2-wire measurement transducer AI_ and MANA - we recommend to jumper them. MANA M Figure 1-14 Connecting 2-wire measurement transducers to the analog inputs of CPU 314 IFM 1 L+ Shielded cables L+ AIU AII AI_ AIU AII AI_ MANA M 4-wire measurement transducer M Unwired channel groups: Connect AI_ with MANA. When using 4-wire measurement transducers, we recommend you interconnect AI_ and MANA.
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CPUs 1.4.5 CPU 315 Technical Specifications of the CPU 315 CPU and Product Version MLFB Data areas and their retentive characteristics 6ES7 315-5AF03-0AB0 Hardware version 01 Firmware version V 1.1.0 Matching programming package STEP 7 V 5.0; Service Pack 03 Retentive data area as a whole (inc. flags, timers, counters) 4736 bytes Bit memories 2048 Memory Work memory Clock memories 8 (1 memory byte) Data blocks max.
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CPUs Configuration Communication functions Rack max. 4 PD/OP communication Yes Modules per module rack max. 8 Global data communication Yes Number of DP masters Number of GD packets integral None – Sender 1 via CP 1 – Receiver 1 S7 message functions Simultaneously active 50 Size of GD packets max. 22 bytes – 8 bytes Alarm-S blocks Time Real-time clock Backed-up Yes Accuracy See Section 1.1.6 Operating hours counter User data per job max.
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CPUs MPI Voltages, Currents Services – PD/OP communication Yes – Global data communication Yes – S7 basic communication Yes – S7 communication Yes (server) Transmission rates 19.2; 187.5 Kbps Dimensions Power supply 24V DC 20.4 to 28.8 V Permissible range Current consumption (idle) typical 7.0 A Inrush current typical 8A l2t 0.4 A2s External fusing for supply lines (recommendation) Circuit breaker; 2 A PD supply at MPI (15 to 30V DC) max.
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CPUs 1.4.6 CPU 315-2 DP DP master or DP slave You can operate the CPU 315-2 DP on your 2nd interface (PROFIBUS-DP interface) as DP Master or DP Slave in a PROFIBUS-DP network. For details on PROFIBUS-DP characteristics of CPU 315-2 DP refer to Chapter 2. CPU 315-2 DP, Technical Data CPU and Product Version MLFB S7 timers 6ES7 315-2AF03-0AB0 Hardware version 01 Firmware version V 1.1.0 Matching programming package STEP 7 V 5.
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CPUs Address areas (I/O) Single sequence Yes Peripheral address area, digital/analog 1 KB/1 KB (freely addressable)of these are Breakpoint 2 Diagnostic buffer Yes 1 KB/1 KB 100 distributed Process image (cannot be customized) 128/128 bytes Digital channels max.
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CPUs Interfaces DP Slave 1. Interface MPI Yes DP Master No DP Slave No Galvanically isolated No MPI – – – 244 bytes I/244 bytes O – max. 32 with max. 32 bytes each Address areas Global data communication Yes Assembly dimension B H T mm S7 basic communication Yes S7 communication Yes (server) Weight Approx. 0.53 kg Programming 19.2; 187.
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CPUs 1.4.7 CPU 316-2 DP DP master or DP slave You can operate the CPU 316-2 DP on your 2nd interface (PROFIBUS-DP interface) as DP Master or DP Slave in a PROFIBUS-DP network. For details on PROFIBUS-DP characteristics of CPU 316-2 DP refer to Chapter 2. CPU 316-2 DP, Technical Data CPU and Product Version MLFB S7 timers 6ES57 316-2AG00-0AB0 Hardware version 01 Firmware version V 1.1.0 Matching programming package STEP 7 V 5.
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CPUs Address areas (I/O) Monitor block Yes Peripheral address area, digital/analog 2 KB/2 KB (freely addressable) Single sequence Yes Breakpoint 2 2 KB/2 KB Diagnostic buffer Yes Process image (cannot be customized) 128/128 bytes 100 Digital channels max. 16384 (minus 1 byte diagnostic address per DP slave)/16384 Communication functions PD/OP communication Yes max. 1024/1024 Global data communication Yes Distributed Centralized Analog channels Centralized max.
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CPUs Interfaces DP Slave 1. Interface Functionality – MPI Yes DP Master No DP Slave No Galvanically isolated No MPI No Services Status/Modify; Program; Routing Yes, can be activated Device master file Siem806f.gsg Transmission rate Up to 12 Mbps Transfer memory 244 bytes I/244 bytes O – max. 32 with max.
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CPUs 1.4.8 CPU 318-2 Special Features 4 accumulators The configuration of MPI interfaces can be changed: MPI or PROFIBUS DP (DP Master). Configurable data areas (Process image, local data) Information on differences between CPU 318-2 and other CPUs is found in Chapter 4.1. DP master or DP slave You can operate the CPU 318-2 DP as DP Master or DP Slave in a PROFIBUS-DP network. However, note that only one of the interfaces can be a DP Slave.
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CPUs FM 353/354, distributed If you implement the CPU 318-2 as DP Master, you can operate FM 353 as of 6ES7 353-1AH01-0AE0, firmware version 3.4/03 and FM 354 as of 6ES7 354-1AH01-0AE0, firmware version 3.4/03 in distributed mode with an ET 200M. You cannot operate the following modules in an S7-300 equipped with a 318-2 CPU FM 357 up to 6ES7 357-4_H02-3AE_, firmware version 2.1; FM NC up to 6FC5 250-3AX00-7AH0, firmware version 3.7 + Toolbox 6FC5 252-3AX2Z-6AB0, Software Version 3.
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CPUs CPU 318-2, Technical Data CPU and Product Version MLFB Data areas and their retentive characteristics 6ES7 318-2AJ00-0AB0 Hardware version 03 Firmware version V 3.0 Matching programming package STEP 7 V 5.1 + Service Pack 02 Retentive data area as a whole (inc. flags, timers, counters) max.
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CPUs Configuration – Rack max. 4 Modules per module rack max. 8 Number of DP masters integral 2 via CP 2 S7 message functions Time Real-time clock Yes User data per job max. 76 bytes – 76 bytes S7 communication Yes (server) User data per job max.
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CPUs DP Master Services – DP Slave Equidistance – SYNC/FREEZE – Activation/deactivat Yes ion of DP slaves Transmission rates Up to 12 Mbps Address area max. 2 KB I/2 KB O User data per DP slave max. 244 bytes I and 244 bytes O Services – Status/Modify; Program; Routing Device master file Yes, can be activated siem807f.gsg Transmission rate Up to 12 Mbps Transfer memory 244 bytes I/244 bytes O 2.
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CPUs 1-74 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2 Introduction In this chapter you will find the features and technical specifications of the CPUs 315-2 DP, 316-2DP and 318-2. You will need these in order to use the CPU as a DP master or a DP slave and configure it for direct communication. Agreement: Since DP Master/Slave behavior is the same for all CPUs, the CPUs described below are referred to as CPU 31x-2.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.1 Information on DPV1 Functionality The aim The EN50170 Standard for Distributed Peripherals was subject to further development. All changes were incorporated in IEC 61158 / EN 50170, Volume 2, PROFIBUS. In order to simplify matters we now refer to DPV1 Mode.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Can I use DPV1 Slaves without this migration? Yes, without restriction. In this case, DPV1 Slaves behave as conventional Slaves. SIEMENS DPV1 Slaves can also be operated in S7 compatible mode. For DPV1 Slaves of other manufacturers you require a GSD file to EN50170 below Revision 3. DPV1 – station-wide. You must convert the complete station to DPV1 mode if you migrate to DPV1. In STEP 7 you can configure this mode in the HW Config module (DP Mode).
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.2 DP Address Areas of the CPUs 31x-2 Address areas of CPUs 31x-2 Address area 315-2 DP 316-2DP 318-2 DP address area for I/Os 1024 bytes 2048 bytes 8192 bytes of these in the I/O process images Bytes 0 to 127 Bytes 0 to 127 Bytes 0 to 255 (default) Can be set up to byte 2047 In the input address area, DP diagnostic addresses occupy 1 byte for the DP master and for each DP slave.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.3 CPU 31x-2 as DP Master Introduction This section covers the features and technical specifications of the CPU when it is used as a DP master. The features and technical specifications of the CPU 31x-2 as the “standard” CPU are listed in Section 1. Prerequisite Should the MPI/DP interface be a DP interface? If so, you must then configure the interface as a DP interface.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Power-Up of the DP Master System CPU 31x-2DP is DP Master CPU 318-2 is DP Master You can also set power-up time monitoring of the DP slaves with the “Transfer of parameters to modules” parameter. Using the parameters “Transfer of parameters to modules” and “Ready message from modules” you can set power-up time monitoring for the DP slaves. This means that the DP slaves must be powered up and configured by the CPU (as DP master) in the set time.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Reading Diagnostic Data with STEP 7 Table 2-2 Reading Diagnostic Data with STEP 7 DP Master CPU 31x-2 Modules or registers in STEP 7 Application See...
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CPU 31x-2 as DP Master/DP Slave and Direct Communication CPU 315-2DP smaller than 6ES7 315-2AF03-0AB0 Diagnostic event OB82 is called Read out the parameter OB 82_MDL_TYPE in the local data of OB 82: The module class is in the bits 0 to 3 (DP slave type) 0011 = DP slave according to the standard 1011 = CPU as DP slave (I slave) Read out OB82_MDL_ADDR Read out OB82_MDL_ADDR (Diagnostic address of the DP slave = STEP 7 diagnostic address) (Diagnostic address of the DP slave = STEP 7 diagnostic addres
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CPU 31x-2 as DP Master/DP Slave and Direct Communication CPU 315-2DP as of 6ES7 315-2AF03-0AB0 CPU 3162DP; Diagnostic event 318-2 OB82 is called only 318-2 Read out OB82_MDL_ADDR and For the diagnostics of the respective modules: Read out OB82_IO_FLAG (= identifier I/O module) call SFB 54 (in DPV1 mode) Set MODE = 1 Diagnostic data is written to Enter bit 0 of OB82_IO_Flag as bit 15 in OB82_MDL_ADDR Result: Diagnostics address ”OB82_MDL_ADDR*” the parameters TINFO and AINFO.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Diagnostic Addresses With a CPU 31x-2, you assign the diagnostic addresses for the PROFIBUS-DP. Make sure during configuration that DP diagnostic addresses are assigned to both the DP master and the DP slave.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Event Detection Table 2-3 shows how a DP Master CPU 31x-2 recognizes operating state transitions of a DP Slave CPU or or data transfer interrupts.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Evaluation in the User Program Table 2-4 shows you how you can, for example, evaluate RUN-STOP transitions of the DP slave in the DP master (see Table 2-3).
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.5 CPU 31x-2 as DP-Slave Introduction This section lists the characteristics and technical specifications for the CPU when it is operated as a DP slave. The characteristics and technical specifications of the CPU as the “standard” CPU can be found in Section 1. Prerequisite Should the MPI/DP interface be a DP interface? If so, you must then configure the interface as a DP interface. Prior to startup, the CPU must be configured as a DP slave.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Status/Control, Programming via PROFIBUS As an alternative to the MPI interface, you can program the CPU via PROFIBUS-DP interface or execute the PG’s Status and Control functions . To do so, you must enable these functions when configuring the CPU as a DP slave in STEP 7. Note The use of Monitor and Modify via the PROFIBUS-DP interface lengthens the DP cycle.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Address areas of the transfer memory Configure the I/O address areas in STEP 7: you can configure up to 32 I/O address areas the maximum length of each one of these address areas is 32 bytes You can configure a maximum of 244 bytes for inputs and 244 bytes for outputs. The table below shows the principle of address areas. You can also find this figure in the STEP 7 configuration.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication S5 DP Master If you are using an IM 308 C as a DP master and the CPU 31x-2 as a DP slave, the exchange of consistent data requires the following: In the IM 308 C, you must program FB 192 to enable the exchange of consistent data between DP master and DP slave.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Sample Program Below you will see a small sample program for the exchange of data between DP master and DP slave. The addresses used in the example are those from Table 2-5.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.6 Diagnosis of the CPU 31x-2 operating as DP-Slave In This Section Section 2-18 Contents Page 2.6.1 Diagnosis with LEDs 2-19 2.6.2 Diagnostics with STEP 5 or STEP 7 2-19 2.6.3 Reading Out the Diagnostic Data 2-20 2.6.4 Format of the Slave Diagnostic Data 2-24 2.6.5 Station Status 1 to 3 2-25 2.6.6 Master PROFIBUS Address 2-27 2.6.7 Manufacturer Identification 2-27 2.6.8 Module Diagnostics 2-28 2.6.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.6.1 Diagnosis with LEDs Diagnostics with LED displays - CPU 31x-2 Table 2-6 explains the meaning of the BUSF LEDs. The BUSF LED assigned to the interface configured as the PROFIBUS-DP interface will always come on or flash. Table 2-6 Meaning of the BUSF LEDs in the CPU 31x-2 as DP Slave Description BUSF Remedy LED off Configuring OK. – LED flashes The CPU 31x-2 is incorrectly configured.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication S7 Diagnosis An S7 diagnosis can be requested for all the modules in the SIMATIC S7/M7 range of modules in the user program. The structure of the S7 diagnostic data is the same for both central and distributed modules. The diagnostic data of a module is in data records 0 and 1 of the system data area of the module. Data record 0 contains 4 bytes of diagnostic data describing the current state of a module.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Example of fetching Slave diagnostic data with FB192 “IM 308C” Here you will find an example of how to use FB192 to fetch slave diagnostic data of a DP slave in the 192 STEP 5 user program. Assumptions The following assumptions are made for this STEP 5 user program: IM 308-C, operating as DP Master, occupies frames 0 ... 15 (number 0 of IM 308-C). The DP Slave has the PROFIBUS address 3.3 The slave diagnostic data should be written to DB20.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication STEP 7 User Program STL Description CALL SFC 59 REQ IOID LADDR RECNUM RET_VAL BUSY RECORD :=TRUE :=B#16#54 :=W#16#200 :=B#16#1 := :=TRUE :=DB 10 Request to Read Identifier of the Address Area, here the I/O input Logical address of the module Data record 1 is to be read out Errors result in the output of an error code Reading process is not finished Destination area for the read data record 1 is data block 10 Diagnostic Addresses With a CPU 31x-
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Event Detection Table 2-8 shows how a DP Master CPU 31x-2 recognizes operating state transitions of a DP Slave CPU or or data transfer interrupts.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.6.4 Format of the Slave Diagnostic Data Structure of Slave Diagnostics Byte 0 Byte 1 Byte 2 Station Status 1 to 3 Byte 3 Master PROFIBUS Address Byte 4 Byte 5 High byte Byte 6 to Byte x Byte x+1 to Byte y Low byte Manufacturer Identification . . . Module Diagnostics (the length depends on the number of address areas configured for transfer memory 1) . . .
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.6.5 Station Status 1 to 3 Definition Station status 1 to 3 provides an overview of the status of a DP slave. Station Status 1 Table 2-10 Structure of Station Status 1 (Byte 0) Bit 0 Description 1: DP slave cannot be addressed by DP master. Remedy Is the correct DP address set on the DP slave? Bus connector plugged in? Does the DP slave have power? RS 485 Repeater setting OK? Execute a Reset on the DP slave.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Station Status 2 Table 2-11 Structure of Station Status 2 (Byte 1) Bit Meaning 0 1: New parameter assignment and configuration of the DP Slave is required. 1 1: A diagnostic message has arrived. The DP slave cannot continue operation until the error has been rectified (static diagnostic message). 2 1: This bit is always “1” when there is a DP slave with this DP address. 3 1: The watchdog monitor has been activated for this DP slave.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.6.6 Master PROFIBUS Address Definition The DP address of the DP Master is written to the diagnostic byte Master PROFIBUS address: The master that has configured the DP slave The master that has read and write access to the DP slave Master PROFIBUS Address Table 2-13 Structure of the Master PROFIBUS Address (Byte 3) Bit 0 to 7 Description DP address of the DP master that configured the DP slave and has read/write access to that DP slave.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.6.8 Module Diagnostics Definition ID related diagnostics specifies in which one of the configured address areas of transient memory an entry was made. Byte 6 7 0 1 0 Bit No. Length of ID-related diagnostic data incl. byte 6 (up to 6 bytes, depending on the number of configured address areas) Code for module diagnosis 7 6 5 4 3 1 Bit No. Byte 7 Default and actual configuration Default and actual config.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.6.9 Station Diagnostics Definition Device diagnostics provides details on a DP Slave. The station diagnosis begins as of byte x and can have a maximum of 20 bytes. Station Diagnostics The figure below describes the structure and content of the bytes for a configured address area in transfer memory. Byte x 7 6 0 0 0 Bit No. Length of the station diagnosis incl. byte x (= max.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication As of byte x +4 The purpose of the bytes beginning with byte x+4 depends on byte x+1 (see Figure 2-8). Byte x+1 Contains the Code for... Diagnostic Interrupt (01H) Hardware interrupt (02H) The diagnostic data contains the 16 bytes of status information from the CPU. Figure 2-9 shows the contents of the first four bytes of diagnostic data. The next 12 bytes are always 0.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.6.10 Interrupts Interrupts with S7/M7 DP Master You can trigger a process interrupt at the DP Master in the user program of a CPU 31x-2 operating as DP Slave. A call of SFC 7 “DP_PRAL” triggers an OB40 in the user program of the DP Master. SFC 7 allows you to forward interrupt information in a DWORD to the DP master; this information can then be evaluated in OB 40 in variable OB40_POINT_ADDR. You can program the interrupt information as desired.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.7 Direct Data Exchange As of STEP 7 V 5.x you can configure “Direct Data Exchange” for your PROFIBUS nodes. The CPU 31x-2 can take part in direct communication as the sender or receiver. “Direct communication” is a special communication relationship between PROFIBUS-DP nodes. Principle Direct communication is characterized by the fact that the PROFIBUS-DP nodes “listen in” to find out which data a DP slave is sending back to its DP master.
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CPU 31x-2 as DP Master/DP Slave and Direct Communication 2.8 Diagnosis with Direct Communication Diagnostic Addresses With direct communication you allocate a diagnostic address on the receiver: CPU 31x-2 as Sender CPU 31x-2 as Receiver PROFIBUS Diagnostic address During configuration you define in the receiver a diagnostic address that is allocated to the sender. The receiver receives information on the status of the sender or on a bus interruption via this diagnostic address (see also Table 2-15).
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CPU 31x-2 as DP Master/DP Slave and Direct Communication Evaluation in the User Program Table 2-16 shows you how you can, for example, evaluate the station failure of the sender in the receiver (see also Table 2-15).
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3 Cycle and Reaction times Introduction In this section, we explain what the cycle time and the response time of the S7-300 consist of. You can use the programming device to read the cycle time of your user program (see the STEP 7 online help system). The example below shows you how to calculate the cycle time. The response time is more important for the process. In this chapter we will show you in detail how to calculate the response time. In This Section Section Contents Page 3.
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Cycle and Reaction times 3.1 Cycle time Cycle Time – A Definition The cycle time is the time that elapses during one program cycle. Component Parts of the Cycle Time The cycle time comprises: Factors Remarks Operating system execution time Process image transfer time (PII and PIO) See Section 3.
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Cycle and Reaction times Extending the Cycle Time Note that the cycle time of a user program is extended by the following: 3.2 Time-controlled interrupt handling process interrupt processing (also refer to Chapter 3.4) Diagnostics and error handling (see also Section 3.4) Communication via MPI Response Time Response Time – A Definition The response time is the time between detection of an input signal and modification of an associated output signal.
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Cycle and Reaction times Shortest Response Time Figure 3-2 shows you the conditions under which the shortest response time is reached. Delay of the inputs Response Time PII Operating system User program PIO The status of the observed input changes immediately before reading in the PII. The change in the input signal is therefore taken account of in the PII. The change in the input signal is processed by the user program here.
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Cycle and Reaction times Longest Response Time Figure 3-3 shows the conditions that result in the longest response time. Delay of the inputs + bus runtime on the PROFIBUS-DP PII Operating system While the PII is being read in, the status of the observed input changes. The change in the input signal is no longer taken into account in the PII. Response Time User program PIO The change in the input signal is taken account of in the PII here.
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Cycle and Reaction times Calculation The (longest) response time consists of the following: 2 Process image transfer time of inputs + 2 Process image transfer time of outputs + 2 Operating system execution time+ 2 program execution time+ 2 Bus runtime on the PROFIBUS-DP bus system (with CPU 31x-2 DP) Execution time of the S7 timer+ Delay of the inputs and outputs This corresponds to the sum of the double cycle time and the delay of the inputs and outputs plus the double bu
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Cycle and Reaction times Table 3-2 Process image update of the CPUs Components CPU 312 IFM CPU 313 CPU 314 CPU 314 IFM CPU 315 CPU 315-2 DP CPU 316-2 DP CPU 318-2 K Base load 162 s 142 s 142 s 147 s 109 s 10 s 10 s 20 s A For each byte in rack “0” 14.5 s 13.3 s 13.3 s 13.6 s 10.6 s 20 s (per word) 20 s (per word) 6 s B For each byte in racks “1 to 3” 16.5 s 15.3 s 15.3 s 15.6 s 12.6 s 22 s (per word) 22 s (per word) 12.
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Cycle and Reaction times PROFIBUS-DP interface In the case of the CPU 315-2 DP/316-2DP, the cycle time is typically extended by 5% when the PROFIBUS-DP interface is used. In the case of the CPU 318-2, there is no increase in cycle time when the PROFIBUS-DP interface is used. Integrated Functions With CPU 312-IFM and 314-IFM operation the cycle time increases by a maximum of 10% when using integrated functions. Also take into consideration a possible instance DB update during the cycle checkpoint.
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Cycle and Reaction times Bus Runtimes in the PROFIBUS Subnet If you have used STEP 7 to configure your PROFIBUS subnet, STEP 7 calculates the expected normal bus cycle time. On the PG you can then view the bus cycle time of your configuration (refer to the STEP 7 User Manual). An overview of the bus runtime is provided in Figure 3-4. In this example, we assume that each DP slave has an average of 4 bytes of data. Bus runtime 7 ms Baud rate: 1.
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Cycle and Reaction times Extending the Cycle by Nesting Interrupts Table 3-6 shows typical extensions of the cycle time through nesting of an interrupt. The program runtime at the interrupt level must be added to these. If several interrupts are nested, the corresponding times need to be added. Table 3-6 Extending the Cycle by Nesting Interrupts Interrupts Hardware interr upt 312 IFM 314 314 IFM 315 315-2 DP 316-2DP 318-2 approx. approx. approx. approx. approx. approx. approx. approx.
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Cycle and Reaction times Sample Configuration 1 You have configured an S7-300 with the following modules on one rack: 1 CPU 314 2 SM 321 DI 32DC 24 V digital input modules (4 bytes each in the PI) 2 SM 322 DO 32 DC 24 V/0.5A (4 bytes each in the PI) According to the Instruction List, the user program has a runtime of 1.5 ms. There is no communication.
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Cycle and Reaction times Parts of the Response Time As a reminder, the response time is formed by the sum of: 2 Process image transfer time of inputs + 2 Process image transfer time of outputs + 2 operating system cycle time+ 2 program cycle time+ Processing time of the S7 timers + Delay times of the inputs and outputs Tip: Simple calculation: calculated cycle time 2 + delay times. Thus, for example one applies: 3.34 ms 2 + timers the I/O modules.
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Cycle and Reaction times 1. Intermediate calculation: Timebase for the calculation of S7 timer processing time is the sum of all times mentioned above: 2 0.36 ms + 2 0.23 ms + 2 1 ms + 2 2.3 ms (Input process image transfer time) (Output process image transfer time) (Operating system cycle time) User program cycle time) 7.8 ms. Processing time of S7 timers Time required for a single update of 56 S7 timers: 56 8 s = 448 s ms. 0.
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Cycle and Reaction times 3.4 Interrupt response time Interrupt Response Time – A Definition The interrupt response time is the time that elapses between the first occurrence of an interrupt signal and the calling of the first instruction in the interrupt OB. Generally valid is: High-priority interrupts are preferred.
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Cycle and Reaction times Diagnostic Interrupt Response Times of the CPUs Table 3-8 lists the diagnostic interrupt response times of the CPUs (without communication). Table 3-8 Diagnostic Interrupt Response Times of the CPUs CPU Min. Max. 312 IFM – – 313 0.6 ms 1.3 ms 314 0.6 ms 1.3 ms 314 IFM 0.7 ms 1.3 ms 315 0.5 ms 1.3 ms 315-2 DP 0.6 ms 1.3 ms 316-2DP 0.6 ms 1.3 ms 318-2 0.32 ms 0.
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Cycle and Reaction times 3.5 Calculation Example for the Interrupt Response Time Parts of the Interrupt Response Time As a reminder: The process interrupt response time is formed by: Response time of the CPU to process interrupt and the response time of the signal module to process interrupt. Example: Your S7-300 assembly consists of a CPU 314 and four digital modules. One digital input module is the SM 321; DI 16 DC 24V; with hardware/diagnostic interrupt configuration.
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Cycle and Reaction times Reproducibility Table 3-9 lists reproducibility of the delay and watchdog interrupts of the CPUs (without communication). Table 3-9 Reproducibility of the Delay and Watchdog Interrupts of the CPUs CPU Reproducibility Delay Interrupt Watchdog Interrupt 314 approx. –1/+0.4 ms approx. 0.2 ms 314 IFM approx. –1/+0.4 ms approx. 0.2 ms 315 approx. –1/+0.4 ms approx. 0.2 ms 315-2 DP approx. –1/+0.4 ms approx. 0.2 ms 316-2DP approx. –1/+0.4 ms approx. 0.
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Cycle and Reaction times 3-18 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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CPU Function, depending on CPU and STEP 7 Version 4 In this chapter we describe the functional differences between the various CPU versions. These differences are determined by CPU performance characteristics (especially CPU 318-2) compared to other CPUs the functionaliy of CPUs described in this manual in comparison to previous versions. Section Contents Page 4.1 Differences between CPU 318-2 and CPUs 312 IFM to 316-2 DP 4-2 4.
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CPU Function, depending on CPU and STEP 7 Version 4.1 Differences between CPU 3182 and CPUs 312 IFM to 3162 DP 4 rechargeable batteries for 318-2 CPU 318-2 CPUs 312IFM to 316-2DP 4 accumulators 2 accumulators The following table shows you what to watch for if you want to use an STL user program of a CPU 312IFM to a CPU 316-2DP for the CPU 318-2.
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CPU Function, depending on CPU and STEP 7 Version System ID (only CPU 318-2) In the object properties of the ”General” tab, you can assign a system ID when configuring your CPU. This ID can be evaluated in the CPU user program (also refer to the STEP 7 Online Help relating to the “General” tab). MPI Addressing CPU 318-2 The CPU addresses the MPI nodes within its configuration (FM/CP) via the module start address.
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CPU Function, depending on CPU and STEP 7 Version S7-300 PG The CPU 316 is replaced with a CPU 318-2 S7-300 S7-300 with CPU 316 S7-300 OP 25 RS 485 repeater OP 25 FM FM FM PG Figure 4-1 Sample Configuration After the CPUs have been swapped, you must proceed as follows (based on the above example): Replace the CPU 316 with the CPU 318-2 in the STEP 7 project. Reconfigure the operator panel/programming device.
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CPU Function, depending on CPU and STEP 7 Version Connection resources CPU 318-2 CPU 318-2 provides a total of 32 communication resources, that is, 32 of those via MPI/DP interface or 16 via DP interface. Those connection resources are freely available for PD/OP communication S7 basic communication S7 communication and Routing of PD communication CPUs 312IFM to 316-2DP The CPUs provide a specific number of connection resources.
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CPU Function, depending on CPU and STEP 7 Version 4.2 The Differences Between the CPUs 312 IFM to 318 and Their Previous Versions Memory Cards and Backing Up Firmware on Memory Card As of the following CPUs: CPU As of Version Order No. Firmware Hardware CPU 313 6ES7 313-1AD03-0AB0 1.0.0 01 CPU 314 6ES7 314-1AE04-0AB0 1.0.0 01 CPU 315 6ES7 315-1AF03-0AB0 1.0.0 01 CPU 315-2 6ES7 315-2AF03-0AB0 1.0.0 01 CPU 316-2 6ES7 316-1AG00-0AB0 1.0.
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CPU Function, depending on CPU and STEP 7 Version MPI Addressing You Have a CPU as of Order Number and Version: Your CPU version and order number is lower than the following: 6ES7312-5AC01-0AB0, version 01 6ES7313-1AD02-0AB0, version 01 6ES7314-1AE03-0AB0, version 01 6ES7314-5AE02-0AB0, version 01 6ES7315-1AF02-0AB0, version 01 6ES7315-2AF02-0AB0, version 01 6ES7316-1AG00-0AB0, version 01 – and STEP 7 V4.02 or later and STEP 7 < V4.
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CPU Function, depending on CPU and STEP 7 Version CPU 315-2 DP v 6ES7 315-2AF03-0AB0 and STEP 7 < V 5.x as of 6ES7 315-2AF03-0AB0 and STEP 7 as of V 5.x Direct communication No Yes Equidistance No Yes Activation/deactivation of DP slaves No Yes Routing No Yes See Figure 2-1 on page 2-8 See Figure 2-2 on page 2-9 CPU 315-2 DP Reading out of slave diagnosis Connection resources From CPU As of Version Order No. Firmware Hardware CPU 312 IFM 6ES7 312-5AC02-0AB0 1.1.
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CPU Function, depending on CPU and STEP 7 Version New SFBs and SFCs in CPU 318-2 Function Block SFB 52 Application Fetching data records to a DP Slave Execution time in ms Initial call 221 Intermediate call 111 SFB 53 SFB 54 Fetching data records to a DP Slave Final call 158 Initial call 284 Second call 110 Final call 110 See...
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CPU Function, depending on CPU and STEP 7 Version Function Block SFC 100* SFC 105* SFC 106 SFC 107 SFC 108 Application Setting TOD and TOD Status Reading dynamic system resources Releasing dynamic system resources Creating block related messages including an acknowledgement function Creating block related messages Execution time in ms MODE 1 274 MODE 2 84 MODE 3 275 MODE 0 MODE 1 MODE 2 117-1832 138-2098 139-1483 MODE 3 140-2128 MODE 1 MODE 2 123-1376 126-1334 MODE 3 125-1407 Initial
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CPU Function, depending on CPU and STEP 7 Version Description of Diverse SFB Execution Times The BUSY output parameter indicates the current job status. Initial call: Job starts with the execution, d. h. BUSY status is toggled from 0 to 1. Intermediate call: The job is being executed, d. h. BUSY retains 1 status. Final call: The job was executed, d. h. BUSY status is reset from 1 to 0. Description of Diverse SFC Execution Times Configure the desired operating mode in your SFCs modes.
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CPU Function, depending on CPU and STEP 7 Version 4-12 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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5 Tips and Tricks Tip on the Parameter “Monitoring time for ...” in STEP 7 Configure the parameters for “Monitoring time for parameter download to module” ready message by module” the highest values if you are not certain of the times required on the S7-300. CPU 31x-2DP is DP Master You can also set power-up time monitoring for the DP slaves with the “Transfer of parameters to modules” parameter.
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Tips and Tricks Without Backup Battery With Backup Battery CPU program on Memory Card or in the integral EPROM of the 312IFM/314IFM All DBs are retentive, whatever configuration has been performed. The DBs generated using SFC 22 “CREAT_DB” are also retentive. Memory card not plugged in All DBs (retentive, The DBs configured as non-retentive) are transferred retentive retain their contents from the memory card or from the integral EPROM into RAM on restart.
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Tips and Tricks CPU 312 IFM and 314 IFM: Erasing the integrated EPROM If you wish to erase the contents of the integrated EPROM, proceed as follows: 1. Open a window with an Online view of the opened project via menu command View Online, or open the Online nodes window per click on the Online nodes in the function bar, or select the menu item PLC Show online nodes. 2. Select the MPI number of the target CPU (double-click). 3. Select the Function Block container. 4. Select the menu item Edit Mark all.
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Tips and Tricks 5-4 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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Standards, Certificates and Approvals A Introduction This Appendix provides the following information on the S7-300 modules and components: The most important standards and criteria met by S7-300 and Approvals that have been granted for the S7-300. IEC 1131 The S7-300 programmable controller meets the requirements and criteria to standard IEC 1131, Part 2.
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Standards, Certificates and Approvals EMC Guidelines SIMATIC products are designed for industrial use. Requirements: Area of Application Industry Emitted interference Immunity EN 50081-2 : 1993 EN 50082-2 : 1995 If you use the S7-300 in residential areas, you must ensure emission of radio interference complies with Limit Class B as per EN 55011.
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Standards, Certificates and Approvals PNO Certificate No. As ...
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Standards, Certificates and Approvals A-4 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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B Dimensioned Drawings Introduction This appendix contains the dimensioned drawings of S7-300 CPUs. The specifications in these drawings are required of you for dimensioning your S7-300 assembly. The dimensioned drawings of the other S7-300 modules and components are contained in the Module Specifications Reference Manual. CPU 312 IFM Figure B-1 shows the dimensioned drawing of CPU 312IFM.
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Dimensioned Drawings CPU 313/314/315/315-2DP/316-2 DP Figure B-2 shows the dimensioned drawing of the CPU 313/314/315/315-2 DP/316-2 DP. The dimensions are the same for all the CPUs listed. Their appearance can differ (see Chapter 1). For example, the CPU 315-2 DP has two LED strips.
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Dimensioned Drawings CPU 318-2 Figure B-3 shows the dimensioned drawing of the CPU 318-2, front view.
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Dimensioned Drawings CPU 314 IFM, Front View Figure B-4 shows the dimensioned drawing of CPU 314IFM, front view. The side view is shown in Figure B-5.
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Dimensioned Drawings CPU 314 IFM, Side View Figure B-5 shows the dimensioned drawing of the CPU 314 IFM, side view.
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Dimensioned Drawings B-6 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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C List of Abbreviations Abbreviations Description STL Statement List (programming language representation in STEP 7) CP Communication processor CPU Central processing unit DB Data block FB Function block FC Function FM Function module GD Global data communication IM Interface module IP Intelligent I/O LAD Ladder logic (programming language representation in STEP 7) FO Fiber-optic cable M Chassis ground MPI Multipoint Interface OB Organization block OP Operator panel PIO O
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List of Abbreviations C-2 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01
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Glossary Accumulator Accumulators are registers in the CPU. They are an intermediate memory for loading, transfer, compare, calculation and conversion operations. Address An address is an ID for a specific operand or operand area, for example: Input I 12.1; memory word MW 25, data block DB 3). Analog module Analog modules convert process values (e.g.
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Glossary Backup memory Backup memory ensures buffering of CPU memory areas CPU, using no battery. A configurable number of timers, counters, memories and data bytes (retentive timers, counters, memories and data bytes) is backed up. Bit memory Memory bits are objects of CPU system memory, used for storing intermediate results. They can be accessed in units of a bit, byte, word or DWORD. Bus A bus is a communication medium connecting several nodes.
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Glossary Code block A SIMATIC S7 code block contains part of the STEP 7 user program. (In contrast: data block only contains data.) Compress The programming device online function “Compress” is used to align all valid blocks contiguously in the RAM of the CPU at the start of the user memory. This eliminates all gaps which arose when blocks were deleted or modified. Communication processor Communication processors are modules for point-to-point and bus links.
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Glossary Cycle time The cycle time represents the time a CPU requires for a single user program execution. Data block Data blocks (DB) are data areas in the user program which contain user data. Global data blocks can be accessed by all code blocks while instance data blocks are assigned to a specific FB call. Data, static Static data is data which can only be used within a function block. The data is saved in an instance data block belonging to the function block.
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Glossary Diagnostic buffer The diagnostic buffer is a buffered memory area in the CPU in which diagnostic events are stored in the order of their occurrence. DP Master A master which behaves in accordance with EN 50170, Part 3 is known as a DP master. DP Slave A DP Slave is operated on a PROFIBUS bus system, using the PROFIBUS-DP protocol and behaves in accordance with EN 50170, Part 3.
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Glossary FB Function block FC Function Flash EPROM FEPROMs are the same as electrically erasable EEPROMS in that they can retain data in the event of a power failure, but they can be erased much more quickly (FEPROM = Flash Erasable Programmable Read Only Memory). They are used on Memory Cards. Force The “Force” function overwrites a variable (e.g. memory marker, output) with a value defined by the S7 user.
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Glossary Functional grounding Grounding which has the sole purpose of safeguarding the intended function of the electrical equipment. Functional grounding short-circuits interference voltage which would otherwise have an impermissible impact on the equipment. GD circuit A GD circuit encompasses a number of CPUs which exchange data by means of global data communication. They are used as follows: A CPU broadcasts a GD packet to the other CPUs. One CPU sends and receives a GD packet from another CPU.
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Glossary Ground (to) To ground means to connect an electrically conducting component to the grounding electrode (one or more conducting components which have a very good contact with the earth) across a grounding system. Instance data block A data block, which is generated automatically, is assigned to each function block call in the STEP 7 user program. The values of the input, output and in/out parameters are stored in the instance data block, together with the local block data.
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Glossary Interrupt, Time-Of-DayThe TOD interrupt belongs to on of the priority classes for SIMATIC S7 program processing. It is generated according to a specified date (or daily) and time-of-day (e.g. at 9:50, hourly, or once a minute). A corresponding organization block is then executed. Isolated The reference potential of the control and load voltage circuits is isolated galvanically in isolated I/O modules; e.g. with optocouplers, relay contacts or transformers.
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Glossary MPI The Multipoint Interface (MPI) represents the SIMATIC S7 programming interface, used to operate multiple nodes (Programming devices, text displays, operator panels) on one or multiple central modules. Each station is identified by a unique address (MPI address). MPI address MPI Nesting depth One block can be called from another by means of block calls. Nesting depth is the number of code blocks called simultaneously.
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Glossary Operating system of the CPU The operating system of the CPU organizes all functions and processes of the CPU which are not associated with a special control task. Parameter 1. STEP 7 code block variable 2. Variable for specifying module behavior (one or several per module). Each module is delivered with a suitable default setting, which can be changed by configuring the parameters in STEP 7.
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Glossary Process image The process image forms part of CPU system memory. The signal states of the input modules are written to the input process image at the start of the cyclic program. At the end of the cyclic program, the signal states in the output process image are transferred to the output modules. Process Interrupt A process interrupt is generated by respective modules, triggered as a result of specific hardware events. The process interrupt is reported to the CPU.
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Glossary RAM A RAM (Random Access Memory, read/write) is a semiconductor chip. Reduction factor The reduction factor based on CPU cycle time determines the frequency of GD package exchange. Reference ground Ground Reference potential Potential with reference to which the voltages of participating circuits are observed and/or measured. Restart When a central processing unit is started up (e.g.
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Glossary Start-up RESTART mode is activated on a transition from STOP mode to RUN mode. Can be triggered with the Mode Selector Switch or after Power On or with a PG operation. With an S7-300 a complete restart is performed. Segment Bus segment SFB System function block (SFB) SFC System function Signal module Signal modules (SM) form the interface between the process and the PLC. There are digital modules digital modules (I/O module, digital) and analog modules (I/O module, analog).
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Glossary System memory System memory is an integrated CPU RAM memory. This system memory contains the operand areas (e.g. timers, counters, memory bits) and data areas required internally by the operating system (e.g. communication buffer). System state list The system status list contains data describing the current status of an S7-300.
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Glossary Time-of-day interrupt Interrupt, time-of-day Token Access right on bus Transmission rate Rate of data transfer (bps) User memory User memory contains Code/Data blocks of the user program. User memory can be integrated in the CPU, on Memory Card or Memory modules. The user program, however, is always processed from CPU main memory. User program SIMATIC differentiates between the CPU operating system and user programs.
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Index Communication-SFBs for configured S7-Connections. See S7-Communication Accumulator, Glossary-1 Compression, Glossary-3 Address, Glossary-1 Configuration, Glossary-3 Address areas, CPU 31x-2, 2-4 Configuration message frame. See in the Analog module, Glossary-1 Internet under the URL Approvals, A-1 http://www.ad.siemens.
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Index CPU 314 IFM, 1-43 basic circuit diagrams, 1-57 integrated functions, 1-43 technical specifications, 1-47 CPU 315, 1-60 2 DP, 1-66 technical specifications, 1-60 CPU 315-2 DP, 1-63 See also CPU 31x-2 DP-Master, 2-5 technical data, 1-63 CPU 316-2 DP, 1-66 See also CPU 31x-2 CPU 318-2, 1-69 See also CPU 31x-2 Communication, 1-69 Differences to other CPUs of the 300 family, 4-2 technical data, 1-71 CPU 31x-2 Bus Interruption, 2-11, 2-23, 2-33 Diagnostic addresses for PROFIBUS, 2-10, 2-22 Direct Data Exch
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Index Forcing, 1-20 Frequency meter CPU 312 IFM, 1-25 CPU 314 IFM, 1-43 Function, FC, Glossary-6 Function block, FB, Glossary-6 Functional grounding, Glossary-7 G Isolated, Glossary-9 L Load memory, Glossary-9 Local data, Glossary-9 M Main memory, Glossary-9 Manufacturer ID, CPU 31x-2 operating as DP-Slave, 2-27 Master-PROFIBUS-Address, 2-27 Memory Backup, Glossary-2 Main-, Glossary-9 user, Glossary-16 memory Load-, Glossary-9 System-, Glossary-15 Memory card, 1-6, Glossary-9 purpose, 1-6 Mode selecto
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Index Runtime meter, CPU, 1-10 P Parameter, Glossary-11 Parameter assignment message frame. See in the Internet under the URL http://www.ad.siemens.
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Index W Watchdog interrupt, reproducibility, 3-17 Watchdog Interrupt, Glossary-8 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01 Index-5
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Index Index-6 PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP A5E00111190-01