Specifications

CPUs

1-45

PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP

A5E00111190-01

Display of the Interrupt Inputs

In variable OB40_POINT_ADDR, you can view the interrupt inputs which have

triggered a process interrupt. Figure 1-9 shows the allocation of the interrupt inputs

to the bits of the double word.

Note: Several bits can be set if interrupts are triggered by several inputs within

short intervals (< 100 s). That is, the OB is started once only, even if several

interrupts are pending.

0 Bit No.

PRIN from I126.0

54 13

31 30

PRIN from I126.1

PRIN from I 126.2

PRIN from I126.3

Reserved

PRIN: Process

interrupt

Figure 1-9 Display of the States of the Interrupt Inputs of the CPU 314 IFM