SINUMERIK 840C SINUMERIK 880/880 GA2 PLC 135 WB/WB2/WD Planning Guide Manufacturer Documentation 12.
SINUMERIK 840C SINUMERIK 880/880 GA2 PLC 135 WB/WB2/WD Planning Guide Manufacturer Documentation Applies to: Control SINUMERIK 840C/CE SINUMERIK 880 T/M SINUMERIK 880 N SINUMERIK 880 G SINUMERIK 880 GA2 T/M 12.
SINUMERIK® documentation Printing history Brief details of this edition and previous editions are listed below. The status of each edition is shown by the code in the ”Remarks” column. Status code in ”Remarks” column: A . . . New documentation B . . . Unrevised reprint with new Order No. C . . . Revised edition with new status. If factual changes have been made on the page since the last edition, this is indicated by a new edition coding in the header on that page. Edition Order No. Remarks 03.
Preliminary Remarks Notes for the reader This manual is intended for the manufacturers of machine tools using SINUMERIK 840C, 880 or 880 GA2. With every new software version, certain functions, conditions, modules etc. are either no longer possible or are added. Parts of this documentation affected by such changes are marked by the following footnotes. The Guide describes in detail the program structure and the operation set of the PLC.
Contents Page 1 Introductory Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.1 1.2 1.2.1 1.2.2 1.3 1.3.1 1.3.2 1.3.3 1.4 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming languages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STEP 5 programming language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-level language programming . . . . . . . . . . . . . . . . . . . . .
5.3.3 5.3.4 5.3.5 5.3.6 5.4 5.4.1 5.4.2 5.5 5.5.1 5.5.2 5.6 5.7 5.7.1 5.8 Special mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semaphore technique within the processing levels of a PLC (LIM/SIM) . Semaphore technique in multiprocessor mode (SES/SEF) . . . . . . . . . . Priority assignment for interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the cyclic program . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 9.3.12 9.3.13 9.3.14 Setting operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and counting operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling operations for timing and counting operations . . . . . . . . . . . . Bit test operations (FB, FX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load and transfer operations . . . . . . . . . . . . . . . . . . . . . . .
12.93 1 Introductory Remarks 1.1 Application 1 Introductory Remarks 1.1 Application The PLC 135 WB/WB2/WD is a powerful interface controller for process automation (controlling, reporting, monitoring). It is integrated in the SINUMERIK 880 / 880 GA2 and SINUMERIK 840C numerical control and controls machine-related functional sequences (auxiliary axes, tool magazines, monitors).
1 Introductory Remarks 1.2.2 High-level language programming 1.2.2 12.93 High-level language programming The tasks of the PLC in a complex machine tool have grown enormously in the past. A highlevel language would be the optimum solution especially when parts of programs contain many branches, jumps and comparisons. It is a quick way of formulating logical expressions which must also be structured so that modules are comprehensible.
11.92 1 Introductory Remarks 1.3.1 Program structure • Function blocks (FBs and FXs) The FBs are used to program frequently recurring complex functions (such as individual controls, reporting, arithmetic and PID control functions). • Sequence blocks (SBs) SBs are special forms of program blocks used primarily for processing sequencers. • Data blocks (DBs and DXs) DBs are used for storing data or texts, and differ in both function and structure from all other block types.
1 Introductory Remarks 1.3.2 Program organization 11.92 Organization, program, function and sequence blocks can invoke other program, function and sequence blocks. The user program cannot call organization blocks. The maximum permissible nesting depth is 62 blocks (all levels, Fig. 1.3), not including an accompanying data block, if any. OB 0 or OB 1 FB PB FB OB 1) PB PB FB FB DB FX PB DX 1) OB 2 ...
11.92 1 Introductory Remarks 1.3.3 Program processing OB 2 OB 3 Process interrupt processing OB 4 Aperiodic triggering OB 5 Timed interrupt processing Fig. 1.4 OB 6 OB 7 Types of interrupt processing There are 2 modes available to the user for interrupting cyclic processing: • Normal mode Here interruption of cyclic processing is only possible at the block limits (Fig. 1.5). If you are working in normal mode, make sure that non-interruptible programs do not require longer than 10 ms.
1 Introductory Remarks 1.4 Differences between the PLC 135 WB2 and the PLC 135 WD 1.4 12.93 Differences between the PLC 135 WB2 and the PLC 135 WD The table below shows the essential differences: PLC 135 WB2 PLC 135 WD Start-up switch (RUN, STOP, GENERAL RESET) No start-up switch (the functions WARM RESTART, COLD RESTART, BOOTSTRAP and GENERAL RESET can only be executed from the programming unit and/or the operator panel).
11.92 2 Program Blocks 2.1 Programming program blocks 2 Program Blocks 2.1 Programming program blocks The information presented in this Section applies to the programming of organization, program and sequence blocks. These three block types are all programmed in the same way (see Section ”Data blocks” and Section ”Function blocks”). Program, organization and sequence blocks can be programmed in all three STEP 5 modes of representation (STL, LAD, CSF) using the basic operations.
2 Program Blocks 2.2 Calling program blocks 2.2 12.93 Calling program blocks Block calls are used to release the blocks for execution (Fig. 2.2). These block calls can be programmed only in organization, sequence, program or function blocks. Organization blocks may not be invoked by the user program, with the exception of OB180. A block call is comparable with a "subroutine branch", and may be both conditional and unconditional.
11.92 3 Data Blocks 3.1 Programming data blocks 3 Data Blocks 3.1 Programming data blocks The data required by the user program is stored in data blocks (DBs and DXs). No STEP 5 operations are programmed in these blocks. Data can be of the following types: • • • Arbitrary bit patterns, e. g. for plant status indications Numbers (hexadecimal, binary, decimal), e. g. for times and results of arithmetic operations Alphanumeric characters, e. g.
3 Data Blocks 3.2 Calling data blocks 3.2 11.92 Calling data blocks Data blocks can be called unconditionally only. Once called, a data block remains in force until the next is invoked. User data blocks must not conflict with those required by the system. A data block call can be programmed in an organization, program, function or sequence block. The "C DB xxx" or "CX DX 200" command calls a data block.
12.93 3 Data Blocks 3.2 Calling data blocks When a program block in which a data block is addressed calls another program block that addresses another data block, the latter is valid only in the program block that was called. The original data block is again valid following return to the calling block (Fig. 3.3). Example 2: Data block 10 is called in program block 7, and the data in this data block are subsequently processed. Program block 20 is then called and executed. Data block 10 is still valid.
3 Data Blocks 3.3 Processing data words greater than data word 255 3.3 11.92 Processing data words greater than data word 255 The size of data blocks was increased from 256 words to 2K words. This gives the user 2043 words as a data field per data block. The corresponding DBs can be generated using the function macro FB 11 (EINR_DB). The system block OB 180 is provided for addressing the additional data words with STEP 5 statements.
12.93 4 Function Blocks 4.1 General remarks 4 Function Blocks 4.1 General remarks Function blocks are used to implement frequently recurring or extremely complex functions. The PLC 135 WB / WB2 / WD interface control also permits function blocks of type FX to be programmed in addition to the previously used function block type FB. The handling of both types is identical. Functions blocks (FBs and FXs) are as much a part of the user program as, for example, program blocks.
4 Function Blocks 4.2 Structure of function blocks 4.2 11.92 Structure of function blocks A function block comprises a block header, name and parameter declaration, and the block body (Fig. 4.1). Block header Name and parameter declarations Block body with STEP 5 program or assembly language statements Fig. 4.1 Structure of a function block 4.2.
12.93 4.3 4 Function Blocks 4.3 Calling and initializing function blocks Calling and initializing function blocks Function blocks (FBs, FXs) are present only once in memory. They can be called once or more than once by a block, and different parameters can be used for each call. Function blocks are programmed or called by specifying a block number (FB 0 to 255 or FX 0 to 255). A function block call can be programmed in an organization, sequence or program block or in another function block.
4 Function Blocks 4.3.2 Parameter list 11.92 PB 3 Call is generated by the programmer Parameter list Call is generated by the programmer Parameter list JU JU I T F Q AI AI JU JU I T F F FB 5 + 5 2.4 5 3.1 6.0 3.2 5.1 FB 5 + 5 5.2 7 3.6 5.0 FB 5 Block header A =PAR 1 O =PAR 2 O =PAR 3 Formal parameters = =PAR 4 BE BE Fig. 4.2 Calling a function block 4.4 Programming function blocks In keeping with its structure, a function block is generated in two parts: the block header and the block body.
11.92 4 Function Blocks 4.4.3 Formal operand (block parameter name) 4.4.3 Formal operand (block parameter name) A formal operand may comprise no more than four characters, the first of which must be a letter. A maximum of 40 parameters can be programmed per function block. STL NAME ZU-E RME ESB UEZ ZEIT ZU-A BEA LSL :JU FB 201 :E-ANTR : DW1 : I 3.5 : F 2.5 : T 2 : KT010.1 : DW2 : Q 2.3 : Q 6.0 Name of the function block Formal operands (names of the block parameters) LAD/CSF FB 201 DW 1 I 3.5 F 2.
4 Function Blocks 4.4.4 Block parameter types 11.92 Operations to which parameters are to be assigned (substitution operations) are programmed in the function block with formal operands. The formal operands may be addressed at various locations within the function block. STL NAME ANNA BERT HANS :JU FB 202 :EXAMPLE : I 13.5 : F 17.7 : Q 23.0 LAD/CSF FB 202 I F 13.5 17.7 ANNA BERT HANS Q 23.
11.92 4.4.5 4 Function Blocks 4.4.5 Block data type and permissible actual operand Block data type and permissible actual operand Parameter type Data type Permitted actual operands I, Q BI for an operand with bit address I Q F n.m inputs n.m output n.
11.92 5 Organization Blocks 5.1 General remarks 5 Organization Blocks 5.1 General remarks The organization blocks form the interface between the system program and the user program. The organization blocks (OBs) are as much a part of the user program as are program blocks, sequence blocks and function blocks, but only the system program can invoke them. A user can only program organization blocks; he cannot invoke them (with the exception of OB 180) (Fig. 5.1).
5 Organization Blocks 5.1 General remarks 12.
12.93 5 Organization Blocks 5.2 Overview Organization block OB 1 must always be available. Organization blocks OB 2 to OB 7 are not mandatory. If they are missing, the call must be disabled by entering the machine data (see Interface Description Part 1: Signals, ”PLC MD bits for basic program”); otherwise the control goes into the STOP state.
5 Organization Blocks 5.3.1 Normal mode 5.3.1 11.92 Normal mode In normal mode the cyclically processed program can only be interrupted at the block limits by interrupt-controlled processing (Fig. 5.2). Only when a change is made from one block to another - either by calling a new block or by returning to a higher-order block after a block end statement - can the system program call up an organization block for interrupt servicing. Organization blocks OB 2 and OB 5 cannot be called up in normal mode.
11.92 5.3.3 5 Organization Blocks 5.3.3 Special mode Special mode In special mode the user program can be interrupted after each MC5 instruction (dependent on PLC MD 6051.0, see Interface Description Part 1: Signals, "PLC MD bits for basic program"). The last command is completed; at the end of the command the timed and process interrupts are enabled. The maximum response time in special mode is therefore reduced to the processing time of a command, if interrupt processing has not yet been activated.
5 Organization Blocks 5.3.4 Semaphore technique within the processing levels of a PLC (LIM/SIM) 11.92 Example: A user program is processed cyclically, during which the lock bit for the OB5 (time interrupt 2.5 ms - time grid) is set. If a timed interrupt occurs in the 2.5 ms time grid, OB5 is not immediately executed by the system program but the request is put in a buffer.
11.92 5 Organization Blocks 5.3.5 Semaphore technique in multiprocessor mode (SES/SEF) Semaphore technique in multiprocessor mode (SES/SEF) 1) 5.3.5 The user has the use of 32 user semaphores; these are used to protect global memory areas in the communication RAM. If two or more PLCs use certain global memory areas in the communication RAM in common, there is a danger that the PLCs might overwrite each other's data or that invalid temporary states of the data may be read out.
5 Organization Blocks 5.3.5 Semaphore technique in multiprocessor mode (SES/SEF) 11.92 Command description: The command "Set semaphore" (SES) sets a byte in the communication RAM assigned to the semaphore for the PLC executing the command (provided it has not already been set by another PLC). As long as this PLC reserves this byte the other PLCs cannot access the area protected by the semaphore. The command "Reset semaphore" (SEF) resets the byte in the communication RAM assigned to the semaphore.
11.92 5.3.6 5 Organization Blocks 5.3.6 Priority assignment for interrupts Priority assignment for interrupts If several interrupts occur simultaneously, the interrupts are processed in the following sequence: OB 1 OB 7 OB 6 OB 5 OB 4 OB 3 OB 2 cyclic processing Increasing priority time-controlled processing aperiodic processing interrupt-controlled processing OB 2 and OB 5 are only processed if PLC machine data bit 6051.0 is 0 (Special mode see Installation Guide, "PLC MD bits for basic program").
5 Organization Blocks 5.4.1 Interface between system program and cyclic program Operating system 11.92 OB 1 1 PB n 2 PB call OB 1 call etc. 5 4 3 BE Operating system Fig. 5.4 BE User program Cyclic program scanning 1 First statement in the STEP 5 program. 2 First PB call. The block called may contain additional calls (cf. Section 1, "Program organization"). 3 Return from the last program or function block executed. 4 The organization block is terminated with BE.
11.92 5.4.2 5 Organization Blocks 5.4.2 Basic program organization Basic program organization Organization block OB 1 contains the basic structure of the user program. A diagram of this block shows the essential program structures at a glance (Fig. 5.5) and emphasizes program-interdependent plant sections (Fig. 5.6).
5 Organization Blocks 5.4.2 Basic program organization OB 1 11.92 PB ”X” Plant section"X" FB Individual control BE JU FB Closed-loop control PB ”X” BE FB Message BE PB ”Y” Plant section"Y" BE FB Sequence control BE JU PB ”Y” FB Message BE PB ”Z” Plant section"Z" BE FB Closed-loop control BE FB Arithmetic JU PB ”Z” BE FB Logging BE Fig. 5.
11.92 5.5 5 Organization Blocks 5.5 Programming the interrupt service routine Programming the interrupt service routine The PLC 135 WB has interrupt-processing capabilities. In this mode, the cyclic program is interrupted and an interrupt service routine executed. Once the interrupt service routine has terminated, the processor returns to the point of interruption and resumes execution of the cyclic program.
5 Organization Blocks 5.5.2 Timeout in process interrupt processing 5.5.2 12.93 Timeout in process interrupt processing Timeout with OB 3 If an edge change is detected on an interrupt byte while OB3 is running, the call request for OB3 is renewed. After OB3 has terminated it is called again. If the operating system detects that an interrupt has already been entered, it signals a timeout (FY 6, bit 3).
12.93 5.6 5 Organization Blocks 5.6 Programming aperiodic processing Programming aperiodic processing With organization block OB 4, blocks can be triggered aperiodically. By calling a defined function macro FB 68 a delay time is started after which OB 4 is called up by the system program. The function macro is defaulted when called with the desired delay time (0-32767 ms). 5.7 Programming timed interrupt processing The processor of the interface control also executes time-controlled processing.
5 Organization Blocks 5.7.1 Interface between system program and time-controlled processing 11.92 Example of processing when several alarms occur: OB 1 PB 17 FB 132 2 JU 1 PB 17 JU 18 13 BE 3 FB 132 11 BE 12 SB 72 5 8 JU SB 72 BE 6 7 BE OB 6 4 BE OB 3 JU 9 FB 8 FB 8 BE BE OB 6 10 BE OB 3 FB 8 15 14 JU FB 8 BE 16 OB 7 17 JU PB 73 PB 73 BE Fig. 5.
11.92 5 Organization Blocks 5.7.
aaa aa aa aa aa a 5 Organization Blocks 5.7.1 Interface between system program and time-controlled processing 10 12.93 aaaaaaaa aaaa After processing of the time-controlled program has been completed, cyclic program processing is resumed as there is no further alarm. aaaaaaaa aaaa A process interrupt occurs: Signal state change at input 0.3. aaaaaaaa aaaa Block change: The process interrupt is registered; cyclic program processing is interrupted.
11.92 5 Organization Blocks 5.8 Calling non-existent blocks Opening a non-existent data block When you attempt to open a non-existent (not loaded) block of type DB or DX, the system program tries to call the organization block OB 19. If OB 19 is present, the value "0" is entered in the system data "current DB" and "DB length" (i.e. no data block has been opened). The user program contained in OB 19 is executed and the interrupted program is continued without an error message.
12.93 6 6 Start-up 6.1 Self-diagnostics program Start-up Starting up of the PLC 135 WB / WB2 / WD is subordinate to the starting up of the numerical machine tool control (NC). The CPUs of the PLC have subordinate functions. When the NC branches into the "Start-up mode overall reset" mode a start-up bit is set. In the NC, deletion and loading of NC and PLC machine data or parameter assignment for the system program can be executed, with the aid of which start-up of PLC 135 WB / WB2 / WD is controlled.
6 Start-up 6.1 Self-diagnostics program 12.
11.92 6.2 6 Start-up 6.2 System initialization program System initialization program After the self-diagnostics program has run, the system initialization program is called. In its first section, the data required for running the organization program are set up.
6 Start-up 6.3 User data blocks 6.3 12.93 User data blocks On each cold restart, certain data blocks are set up and written in ascending order into the user data segment. A list of these data blocks is contained in the INTERFACE DESCRIPTION PART 1: SIGNALS of the control concerned. Data blocks DB 30 to DB 71 are defaulted with 0. The channel, spindle and axes data blocks are defaulted with the user data if they are enabled for writing (see INTERFACE DESCRIPTION, PART 1: SIGNALS).
11.92 7 7 Device Error Analysis 7.1 Interrupt stack Device Error Analysis The system program can ascertain faulty operation of the central processor, errors in the system program or the effect of erroneous programming. If the interpreter ascertains an error in command execution or if another error occurs causing program interruption, a branch is made into the STOP loop. 7.1 Interrupt stack The programmer's ”Output ISTACK” function can be invoked to help analyze errors.
7 Device Error Analysis 7.1 Interrupt stack BARB BARBEND KEINPS UAFEHL MAFEHL EOVH OBWIED KOPFNI PADFRE ASPLUE RAMADFE EAADFE SYNFEH NINEU NIWIED RUFBST SUMF URLOE STS STP 7–2 11.
12.93 7 Device Error Analysis 7.1 Interrupt stack The following can be called to screen as the next display: PLC INFORMATION DEPTH: ISTACK 01 BEF-REG: 13E0 SAZ: 35F3A BST-STP: 00004 XX-NR.r: 38 AKT REL-SAZ: 0004A OB-NR.: 1 BEF-Z: ACCU1: 76B1 0000 ACCU2: 0000 E45C RESULT COND. COD.: ANZ1 ANZ0 X STATUS VKE X DB-ADR: 065F0 DB-NR.: 23 DBL-REG: 99 CAUSE OF FAULT: BR-ADR: YY-NR.
7 Device Error Analysis 7.1 Interrupt stack 12.93 See Section EVENT FLAGS OF THE PLC 135 WB/WB2/WD for the meaning of the result condition codes.
12.93 7 Device Error Analysis 7.2 Detailed error code 7.2 Detailed error code Using the programmer's info function, the user can display additional information for interrupt analysis by entering pseudo address F0000hex.
7 Device Error Analysis 7.2 Detailed error code zob2 zob3 zob4 zob5 zob6 zob7 = = = = = = 12.
12.93 8 Memory Allocation and Organization 8.1 Segment allocation 8 Memory Allocation and Organization 8.1 Segment allocation The expanded memory area of the PLC 135 WB/WB2/WD interface control can be addressed directly with the new programmer software. The segment switch is no longer required.
8 Memory Allocation and Organization 8.1 Segment allocation 12.
12.93 8 Memory Allocation and Organization 8.1 Segment allocation Memory allocation 1 System data memory 64 KByte User data memory 64 KByte User program memory 1 64 KByte aaaaaaaaaa aaaaaaaaaa 5 and 6 9 10 User program memory 2 64 KByte 11 User program memory 3 64 KByte 12 User program memory 4 64 KByte 7 System program 128 KByte memory 8 Table 8.
8 Memory Allocation and Organization 8.2 Segment switch 11.92 8.2 Segment switch 8.2.1 Changing the segment switch The following sequence applies to the PG 685 programmer: • • • • • Call the information functions with the F5 key Call any memory areas with the F1 key Enter the pseudo-address E0000hex Press the Enter key Press the Abort key The first word shown is the current setting of the segment switch. • • Press the correction key Enter the new segment address 8.2.
11.92 8 Memory Allocation and Organization 8.3 Block lists The following should be observed with regard to output of the block lists via the address list: • The first address of the address list entry is the offset address; the second one is the segment address. • High and low bytes are interchanged in the specified address. • The offset addresses are word-oriented, except that the enteries of the DB list are byteoriented; these must be divided by two after the high/low swap.
11.92 9 STEP 5 Operation Set with Programming Examples 9.1 General notes 9 STEP 5 Operation Set with Programming Examples 9.1 General notes The STEP 5 operation set is subdivided into basic operations and supplementary operations. The basic operations are intended for the execution of simple binary functions. As a rule, they can be input/output in the three methods of representation (LAD,CSF and STL) of the STEP 5 language on the programmer.
9 STEP 5 Operation Set with Programming Examples 9.1.1 Numeric representation 11.92 • Fixed-point double-word: 0 ... +2 147 483 647 – 1 ... – 2 147 483 648 The fixed-point double-word is located in the ACCU and is interpreted as a 32-bit binary number in two's complement representation. • Floating-point number: m . 2exp m = Mantissa exp = Exponent ±0.1 701 412 · 1039 ±0.
12.93 9 STEP 5 Operation Set with Programming Examples 9.1.2 Condition codes of the PLC 135 WB/WB2/WD 9.1.2 Condition codes of the PLC 135 WB/WB2/WD There are commands for processing individual bit information, and there are commands for processing word information (8, 16 or 32 bits). In both groups, there are commands which set condition codes and commands which interpret condition codes. For both command groups there are "condition codes for bit operations" and "condition codes for word operations".
9 STEP 5 Operation Set with Programming Examples 9.2 Basic operations 9.2 11.92 Basic operations Basic operations are programmable in program, sequence, organization and function blocks. They can be input and output in program, sequence and organization blocks in the three methods of representation (LAD, CSF and STL). In the function blocks, the operations are only displayed in the statement list. Exceptions: 1.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.1 Logic operations, binary AND operation Given circuit Control system list flowchart A A A = I 1.1 1.3 1.7 I1.1 I1.3 & STEP 5 representation Statement Ladder diagram I I I Q 1.1 1.3 1.7 3.5 I1.1 I1.3 I1.7 Q3.5 I1.1 & I1.3 I1.7 Q3.5 I1.7 Q3.5 Q 3.5 A logic 1 appears at output Q 3.5 if all inputs are simultaneously at logic 1. A logic 0 appears at output Q 3.5 if at least one of the inputs is at logic 0.
9 STEP 5 Operation Set with Programming Examples 9.2.1 Logic operations, binary 11.92 AND before OR operation Given circuit I1.5 I1.6 I1.4 & I1.3 & I1.5 I1.4 I1.6 I1.3 STEP 5 representation Statement Ladder diagram Control system list flowchart A A O A A = I I I1.5 1.5 1.6 I1.4 I1.6 Q3.1 I1.5 & I1.6 I1.3 I 1.4 I 1.3 Q 3.1 I1.4 >=1 & Q3.1 I1.3 Q 3.1 1 Q 3.1 A logic 1 appears at output Q 3.1 if at least one AND condition is fulfilled. A logic 0 appears at output Q 3.
12.93 9 STEP 5 Operation Set with Programming Examples 9.2.1 Logic operations, binary OR before AND operation Given circuit I1.4 I1.5 I2.0 1 1 I1.5 I2.0 I2.1 Control system list flowchart A( O O ) A( O O ) = I2.1 I1.4 STEP 5 representation Statement Ladder diagram Q 3.0 & I I 1.4 1.5 I I 2.0 2.1 I1.4 I2.0 I1.5 I2.1 Q3.0 I1.4 1 I1.5 & I2.0 1 Q3.0 I2.1 Q 3.0 Q 3.0 A logic 1 appears at output Q 3.0 if both OR conditions are fulfilled. A logic 0 appears at output Q 3.
9 STEP 5 Operation Set with Programming Examples 9.2.2 Storage operations 11.92 RS flipflop for latching signal output Given circuit I1.4 I2.7 R I1.4 I2.7 S 1 1 1 0 STEP 5 representation Statement Ladder diagram Control system list flowchart A S A R I Q I Q 2.7 3.5 1.4 3.5 I2.7 I1.4 Q3.5 Q3.5 S I2.7 S RQ I1.4 RQ Q3.5 Q3.5 A logic 1 at input I 2.7 causes the flipflop to be set. If the logic level at input I 2.7 changes to 0, this state is retained, i.e. the signal is stored.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.2 Storage operations Simulation of a momentary-contact relay Given circuit STEP 5 representation Statement Ladder diagram Control system list I1.7 A AN = A S AN R I1.7 F4.0 F2.0 F2.0 flowchart I F F F F I F 1.7 4.0 2.0 2.0 4.0 1.7 4.0 I1.7 F4.0 F2.0 F4.0 I1.7 S F4.0 R & F2.0 S I1.7 Q R Q The AND condition (A I 1.7 and AN F 4.0) is fulfilled with each leading edge of input I 1.7; flags F 4.0 ("signal edge flag") and F 2.
9 STEP 5 Operation Set with Programming Examples 9.2.3 Load and transfer operations 9.2.3 11.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.
9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations 9.2.4 11.92 Timing and counting operations In order to load a timer or counter with a set command, the value must be loaded in the accumulator beforehand.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations Pulse Given circuit I3.0 S 10s 1 Control system list flowchart A L SP A = I3.0 R STEP 5 representation Statement Ladder diagram I 3.0 KT 10.2 T 1 T 1 Q 4.0 T1 T10 I3.0 1 I 3.0 1 DU DU 10.2 TW 10.2 TW DE R Q DE T1 T1 Q4.0 Q Q4.0 Q4.0 Q4.0 With the first execution, the timer is started if the result of the logic operation is 1. If execution is repeated with RLO = 1, the timer is unchanged.
9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations 11.92 Extended pulse Given circuit STEP 5 representation Statement Ladder diagramn Control system list flowchart I3.1 T2 A L SE A = I3.1 R S T2 T2 1 I 3.1 IW15 T 2 T 2 Q 4.1 T2 I3.1 1 V I 3.1 1 V DU DU IW15 TW IW15 TW DE R Q DE T2 Q4.1 Q4.1 R Q Q4.1 Q4.1 With first execution, the timer is started if the result of the logic operation is 1. If the RLO = 0 the timer is unchanged.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations ON-delay Given circuit STEP 5 representation Statement Ladder diagram Control system list flowchart I3.5 R S 9s 0 T3 A L SD A = I3.5 I 3.5 KT 9.2 T 3 T 3 Q 4.2 T3 I3.5 T 0 T 0 DU DU K9.2 K9.2 TW TW DE R Q DE T3 T3 Q4.2 R Q4.2 I 3.5 Q Q4.2 Q4.2 With the first execution, the timer is started if the result of the logic operation is 1.
9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations 11.92 OFF-delay Given circuit I3.4 0 S t Control system list flowchart AN L SF A = I3.4 R STEP 5 representation Statement Ladder diagram I3.4 T5 I 3.4 FW13 T 5 T 5 Q 4.4 T5 I3.4 0 T I 3.4 0 T DU DU FW13 TW FW13 TW DE R Q DE T5 T5 Q4.1 R Q4.4 Q Q4.4 Q4.4 With the first execution, the timer is started if the result of the logic operation is 0.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations Latching ON-delay Given circuit I3.2 STEP 5 representation Statement Ladder diagram Control system list flowchart I3.3 A L SS A R A = I3.3 R S 20s T4 0 I3.2 T4 T4 T4 I 3.3 DW21 T 4 I 3.2 T 4 T 4 Q 4.3 T4 I3.3 T s I 3.3 T s DU DU DW21 DW21 TW TW DE R Q DE Q4.3 I3.2 R Q I3.2 Q4.3 Q4.3 Q4.3 With the first execution, the timer is started if the result of the logic operation is 1.
9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations 11.92 Setting a counter Given circuit I4.1 R S IW20 STEP 5 representation Statement Ladder diagram Control system list flowchart A L S CI C1 I 4.1 IW20 C 1 C1 CU CU CD CD I4.1 S + CQ Binary 16 bits IW20 CV I4.1 DU IW20 S CV DE R DU DE R Q Q With the first execution, the counter is set if the result of the logic operation is 1.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations Resetting a counter Given circuit Control system list flowchart C1 I4.2 R STEP 5 representation Statement Ladder diagram S A R A = CI I C C Q 4.2 1 1 2.4 = 0 CQ CU CD CD S S CV IW20 Binary 16 bits C1 CU CV DU DU DE DE Q2.4 I4.2 Q2.4 R Q R I4.2 Q Q2.4 If the result of the logic operation is 1 the counter is set to zero (cleared).
9 STEP 5 Operation Set with Programming Examples 9.2.4 Timing and counting operations 11.92 Down counting Given circuit STEP 5 representation Statement Ladder diagram Control system list flowchart C1 I4.0 A I 4.0 CD C 1 R I4.0 S CI - CQ I4.0 CD CU CU S S CV Binary 16 bits C1 CD DU CV DE R DU DE Q R Q The value of the addressed counter is decremented by 1. The function only becomes effective with a positive-going edge (from 0 to 1) of the logic operation programmed before CD.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.5 Comparison operations Compare for equal Given circuit IB19 STEP 5 representation Statement Ladder diagram Control system list flowchart IB20 C1 L L != = C2 IB19 IB20 F Q 3.0 IB19 C1 F IB19 C1 != F != Q3.0 IB20 C2 Q C2 IB20 Q Q3.0 Q3.0 The operand first specified is compared with the next operand according to the comparison function. The comparison results in a binary result of the logic operation.
9 STEP 5 Operation Set with Programming Examples 9.2.5 Comparison operations 11.92 Compare for greater Given circuit IW3 STEP 5 representation Statement Ladder diagram Control system list flowchart FD5 C1 L L > = C2 > < IW3 FD5 D Q 3.2 IW3 D IW3 C1 > D > Q3.2 FD5 > C1 C2 Q C2 FD5 Q Q3.2 < Q3.2 The operand first specified is compared with the next operand according to the comparison function. The comparison results in a binary result of the logic operation.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.5 Comparison operations Compare for greater than or equal to Given circuit DD10 DD20 C1 C2 STEP 5 representation Statement Ladder diagram list L DD10 L DD20 >=G = > < DD10 G DD10 C1 >= G > Q3.3 DD20 > C1 Control system flowchart C2 Q C2 DD20 Q Q3.3 < Q3.3 The operand first specified is compared with the next operand according to the comparison function. The comparison results in a binary result of the logic operation.
9 STEP 5 Operation Set with Programming Examples 9.2.6 Block calls 9.2.6 11.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.6 Block calls Unconditional call for a function block Given circuit PB 101 FB 72 . . . . . . JU . . . . FB72 STEP 5 representation StatementLadder diagram Control system list flowchart . . . JU FB 72 . . . FB 72 FB 72 . . . . . . BE BE The unconditional function block call is entered at the desired program point. With graphic methods of representation LAD and CSF, the called block (FB, FX) is represented as a box.
9 STEP 5 Operation Set with Programming Examples 9.2.7 Code operations 9.2.7 11.92 Code operations The code operations allow a time or count, which is present in binary from, to be loaded as a code in the accumulator; the corresponding value is still available in BCD form for further processing. Operation Parameter LC Function Load as code T C 0 to 255 0 to 255 times counts Loading a time (coded) Given circuit STEP 5 representation StatementLadder diagram list T10 Load A L SP LC T I 5.
11.92 9 STEP 5 Operation Set with Programming Examples 9.2.8 Arithmetic operations 9.2.8 Arithmetic operations Arithmetic operations can only be represented in the statement list. They process the contents of Accumulators 1 and 2. Suitable load operations, for example, are required.
9 STEP 5 Operation Set with Programming Examples 9.2.9 Other operations 9.2.9 11.92 Other operations The following operations can only be represented in a statement list. Operation STP NOP 0 NOP 1 BLD Parameter Function 0 to 255 Stop No operation (all bits cleared) No operation (all bits set) Screen command The STOP command is used, for example, when the PLC is required to go to the stop state in the event of certain critical states of the system or when a device error occurs.
11.92 9 STEP 5 Operation Set with Programming Examples 9.3.1 Logic operations, binary 9.3.
9 STEP 5 Operation Set with Programming Examples 9.3.3 Timing and counting operations 9.3.3 12.
11.92 9 STEP 5 Operation Set with Programming Examples 9.3.3 Timing and counting operations Examples: Function block call NAME ANNA BERT JACK : JU FB203 : EXAMPLE : I 10.3 : T 17 : Q 18.4 NAME MAXI IRMA EVA DORA EMMA : JU FB204 : EXAMPLE : I 10.5 : I 10.6 : I 10.7 : C 15 : F 58.3 NAME CURT CARL PETE CUTE : JU FB205 : EXAMPLE : I 10.4 : T 18 : IW20 : F 100.7 Program in function block Program executed :A :L : SSU :A := = ANNA KT 010.2 = BERT = BERT = JACK :A :L : SS :A := I 10.3 KT 010.
9 STEP 5 Operation Set with Programming Examples 9.3.4 Enabling operations for timing and counting operations 9.3.4 11.92 Enabling operations for timing and counting operations Operation Description FR T 0 to 255 Enabling a time for a restart The operation is only executed with a leading edge of the result of the logic operation. It initiates a restart of the time if the RLO present is 1 for the start operation.
11.92 9 STEP 5 Operation Set with Programming Examples 9.3.5 Bit test operations (FB, FX only) 9.3.5 Bit test operations (FB, FX only) Operation Parameter TB TBN SU RU Function Test the bit for logic 1 Test the bit for logic 2 Set bit unconditionally Reset bit unconditionally I 0.0 to 127.7 an input Q 0.0 to 127.7 an output F C T D 0.0 to 255.7 0.0 to 255.15 0.0 to 255.15 0.0 to 255.15 a flag a count word a time word a data word Operations "P" and "PN" are scans.
9 STEP 5 Operation Set with Programming Examples 9.3.6 Load and transfer operations 9.3.6 11.92 Load and transfer operations Operation Description L = Load a formal operand The value of the operand specified as a formal operand will be loaded into the ACCU (parameters: I, Q; parameter type: BY W, D). LD= Load a formal operand as code The value of the timer or counter specified as a formal operand will be loaded into the ACCU in BCD form (parameters: T, C).
11.92 9 STEP 5 Operation Set with Programming Examples 9.3.7 Logic operations, digital 9.3.7 Logic operations, digital Operation Description AW OW XOW AND operation, digital, ACCU 1 and ACCU 2 OR operation, digital, ACCU 1 and ACCU 2 Exclusive OR operation, digital, ACCU 1 and ACCU 2 ACCU 1 and ACCU 2 can be loaded according to the operands of the load operation, by means of two load operations. The contents of both accumulators can then be subjected to a digital operation.
9 STEP 5 Operation Set with Programming Examples 9.3.9 Conversion operations 9.3.9 11.
11.92 9 STEP 5 Operation Set with Programming Examples 9.3.11 Jump operations 9.3.11 Jump operations The jump destination for unconditional and conditional jumps is specified symbolically (maximum of 4 characters): the symbolic parameter of the jump command is identical with the symbolic address of the statement to be jumped to. When programming, ensure that the unconditional jump distance is not more than ± 127 words. If should be noted that a STEP 5 statement must not comprise more than one word.
9 STEP 5 Operation Set with Programming Examples 9.3.11 Jump operations 11.92 Operation Description JOS = The jump will be executed if "Overflow stored" is set (OS = 1) Otherwise (OS = 0) the jump will not be executed. "Overflow stored" will be set for arithmetic operations in the event of an overflow, and will remain stored until the arithmetic operation is interrupted. An overflow exists when, with numeric representation, the permissible range is exceeded by an arithmetic operation.
11.92 9 STEP 5 Operation Set with Programming Examples 9.3.
9 STEP 5 Operation Set with Programming Examples 9.3.12 Processing operations 11.92 9.3.12 Processing operations Operation Description DO= Process formal operand (type of parameter: DO) Insert formal operand Only the following operations can be substituted: C DB JU PB JU SB JU FB (See Section "Type of block parameter and allowed actual operand”) DO DW 0 to 255 (Operation) Process data word The specified operation which follows will be combined with the parameter given in the data word and executed.
11.92 9 STEP 5 Operation Set with Programming Examples 9.3.12 Processing operations • If Q 4.1 is to be set, the value KH0184 (pointer + KH0000) must be stored in the pointer word. • In the specification of command F, the two expressions SU I 0.0 or SU Q 0.0 are fully equivalent. • Any self-programmed bit address in the command (e.g. SU I 4.7) will be ignored. Example: Process data word The contents of data words DW 20 to DW 100 are to be deleted.
9 STEP 5 Operation Set with Programming Examples 9.3.13 Operations for page memory processing 12.93 9.3.
12.93 9 STEP 5 Operation Set with Programming Examples 9.3.14 Other operations 9.3.
9 STEP 5 Operation Set with Programming Examples 9.3.14 Other operations 12.93 If you want to calculate back within a block, you must use the instructions "L KF+" and "– D". Example: ACCU1 0006 6002 0000 0002 0006 6000 L L – MD 240 KF +2 D • With instructions LIR 0 and TIR 2 the parameters will not be verified, i.e. any value can be programmed. No error message appears. In the case of commands with direct memory access (LIR, TIR, TNB, TNW) an offset and a segment address are required.
12.93 9 STEP 5 Operation Set with Programming Examples 9.3.14 Other operations The following applies when defaulting the offset address: LIR, TIR, TBW: TNB: Defaulting word address Defaulting byte address Example: L KB 6 T FW 250 L KH 0100 T FW 252 L MD 250 LIR 0 Offset address for DWx Load DWx See Section "Block lists" for the direct processing of the block list with the instructions LIR and TIR.
11.92 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.1 General 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.1 General What you can do with each method of representation in the STEP 5 programming language has its limits.
10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.2 Rules of compatibility for graphic program input (LAD, CSF) 10.2 11.92 Rules of compatibility for graphic program input (LAD, CSF) Excessively deep nesting can result in the display limits (8 levels) being exceeded in the CSF. LAD INPUT 1 INPUT 2 INPUT 4 INPUT 6 OUTPUT INPUT 3 INPUT 5 INPUT 7 CSF INPUT 1 & >=1 INPUT 2 & >=1 INPUT 3 & INPUT 4 INPUT 5 >=1 INPUT 6 INPUT 7 Fig. 10.
11.92 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.2 Rules of compatibility for graphic program input (LAD, CSF) Input in CSF: Output in LAD and STL Rule 1: Do not exceed the display limits for LAD: An excessive number of inputs at a CSF box results in exceeding the LAD display limit. CSF INPUT INPUT INPUT INPUT INPUT INPUT INPUT & 1 2 3 4 5 6 7 OUTPUT LAD INPUT 1 Fig. 10.
10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.2 Rules of compatibility for graphic program input (LAD, CSF) 11.92 Rule 3: Connectors • • Connectors are always allowed with an OR-box. Connectors are only allowed at the first input with an AND-box. (Connectors are intermediate flags which are used for economy with recurring logic operations). # X Fig. 10.
11.92 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list 10.3 Rules of compatibility for program input in a statement list Rule 1: AND operation: (Test of logic state and AND logic). LAD: LAD: Contact in series CSF: & CSF: Input to an AND-box STL: A . . . . STL: Statement A . . .
10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list STL : : : : : : A A O O A A . . . Fig. 10.9 INPUT 1 INPUT 2 INPUT 3 INPUT 4 INPUT 5 LAD INPUT 1 CSF INPUT 2 >=1 INPUT 3 INPUT 4 INPUT 5 & INPUT 4 INPUT 5 Explanations of the rule for OR operations 1st parallel branch Next parallel branch(es) LAD LAD: Two or more contacts in a parallel branch CSF CSF: AND-box before OR-box O ... A ... A ...
11.92 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list Rule 4: Parentheses Covered in this rule are the parenthesized, complex, enclosed binary operations or complex elements with prior or subsequent operations.
10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list 11.92 b) Complex elements (storage, timing, comparison and counting functions) The following rules must be observed for complex elements: No subsequent operation, no parentheses Subsequent operation AND: A (. . .) . . . Subsequent operation OR: O (. . .) . . . (only for CSF, not allowed for LAD) A complex element cannot have prior operations.
11.92 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.
10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list 11.92 NOP O must be applied to each unused input or output. Exception: S and TV for timers, and S and CV for counters must always be used jointly. For STL programming, the complex elements must be programmed in the same order as the parameter assignment on the screen in the graphic method of representation.
11.92 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.
10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list Case 1: INPUT 2 INPUT 3 & & 11.92 INPUT 8 INPUT 9 & INPUT 4 Case 2: INPUT 1 INPUT 5 >=1 >=1 >=1 INPUT 6 Case 3: INPUT 2 INPUT 7 & >=1 >=1 INPUT 3 INPUT 8 INPUT 9 Case 4: INPUT 1 INPUT 5 & >=1 & & >=1 INPUT 6 >=1 & INPUT 7 Fig. 10.
11.92 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list Rule 5: Connectors For the sake of clarity, the rules for connectors are listed separately for the LAD and CSF methods of representation. The following example is given for both. LAD STL F. . . : A = F. . . # : = = F. . . Fig. 10.
10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list STL CSF # F... 11.92 := = F... :A = F... Fig. 10.19 The connector in CSF and STL b) Connectors with CSF The result of the entire binary logic operation before the connector is buffered in the connector. The following rules apply: • Connector at the first input of an AND or OR-box: The connector is transformed without parentheses.
11.92 10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list Examples for connectors: Two examples are given: One without and one with connectors.
10 Rules of Compatibility between the LAD, CSF and STL Methods of Representation 10.3 Rules of compatibility for program input in a statement list 11.
Operating Fig. 11.
11 Hardware 11.1.1 Operating the PLC 135 WB/WB2 using the mode switch 12.93 11.1.1 Operating the PLC 135 WB/WB2 using the mode switch On the front panel of the interface controller is a mode switch with the positions RUN (R), STOP (S) and OVERALL RESET (U). With this switch various modes can be produced.
12.93 11 Hardware 11.1.1 Operating the PLC 135 WB/WB2 using the mode switch Operation LED signal state PLC response Comment With the change from STOP O. RESET an overall reset is requested. The LEDs blink Overall reset with synchronously at a frequency bootstrapping of the user of 1 sec. The reset request is program and the data from STOP tv>2 sec. With the second change from STOP O. RESET indicated by fast asynchronous blinking of both LEDs. After the the EPROM.
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12.93 11 Hardware 11.2.1 Operating the PLC 135 WD 11.2.1 Operating the PLC 135 WD The PLC 135 WD no longer has a start-up switch. The functions WARM RESTART, COLD RESTART, BOOTSTRAP and GENERAL RESET can be executed from the programming unit and/or the operator panel (see INSTALLATION INSTRUCTIONS). Notes: • S5 functions (e.g.
12.93 12 Programming and Test Functions with the Programmer 12.1 Requirement 12 Programming and Test Functions with the Programmer 12.1 Requirement To be able to use the full power of the PLC 135 WB/WB2/WD, the following programmers are used with the appropriate software.
12 Programming and Test Functions with the Programmer 12.3 START PLC 12.3 12.93 START PLC The following restart modes can be selected via the programmer screen form START PLC: NEUSTART (cold restart) The PLC performs a cold restart. WIEDERANLAUF (warm restart) The PLC performs a warm restart. A warm restart is, however, only possible if the PLC has been put into the stop state by the function STOP PLC.
12.93 12 Programming and Test Functions with the Programmer 12.4 Block handling using the programmer 12.4 Block handling using the programmer Programmer operation OVERALL RESET Result in the PLC Comment All user program blocks and data blocks are deleted PLC must be in the STOP (RAM memory). Then the user EPROMs are automatically bootstrapped. state.
