Microcomputer Components SAB 80C517A/83C517A-5 8-Bit CMOS Single-Chip Microcontroller Addendum to User's Manual SAB 80C517/80C537 05.
Edition 05.94 This edition was realized using the software system FrameMaker. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1994. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
SAB 80C517A/83C517A-5 Revision History: 05.94 Previous Version: 11.92 Page Subjects (major changes since last revision 11.92) 3-8 4-1 5-3 5-10/5-11 S0RELL adresses corrected HWPD pin number corrected TS/TC in table 5-1 corrected CC4EN bit names and table 5-3 corrected Device Specifications SAB 80C517A/83C517A-5 Revision History: 05.94 Previous Releases: 01.94/08.93/11.92/10.91/04.91 Page Subjects (changes since last revision 04.
80C517A/83C517A-5 Contents Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Program Memory, ROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Data Memory .
Introduction 1 Introduction The SAB 80C517A is a superset of the high end microcontroller SAB 80C517. While maintaining all architectural and operational characteristics of the SAB 80C517 the SAB 80C517A incorporates more on-chip RAM as well as some enhancements in the compare / capture unit. The oscillator watchdog got an improved functionality. Also the operating frequency is higher than that of the SAB 80C517.
Introduction Listed below is a summary of the main features of the SAB 80C517A: ● SAB 80C517A/83C517A-5, up to ● ● ● ● ● ● ● ● Fast 32-bit division, 16-bit multiplication, 32- 18 MHz operation frequency 32 K×8 ROM (SAB 83C517A-5 only, ROMProtection available) 256×8 on-chip RAM 2K×8 on-chip RAM (XRAM) Superset of SAB 80C51 architecture: – 1 µs instruction cycle time at 12 MHz – 666 ns instruction cycle time at 18 MHz – 256 directly addressable bits – Boolean processor – 64 Kbyte external data and progra
Fundamental Structure 2 Fundamental Structure The SAB 80C517A/83C517A-5 is a high-end member of the Siemens SAB 8051 family of microcontrollers. It is designed in Siemens ACMOS technology and based on the SAB 8051 architecture. ACMOS is a technology which combines high-speed and density characteristics with low-power consumption or dissipation. While maintaining all the SAB 80C517 features and operating characteristics the SAB 80C517A is expanded in its "fail-safe" characteristics and timer capabilities.
Fundamental Structure Figure 2-1, Block Diagram of the SAB 80C517A Semiconductor Group 2-2
Memory Organization 3 Memory Organization According to the SAB 8051 architecture, the SAB 80C517A has separate address spaces for program and data memory. Figure 3-1 illustrates the mapping of address spaces.
Memory Organization 3.1 Program Memory, ROM Protection The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA controls whether program fetches below address 8000H are done from internal or external memory. As a new feature the SAB 83C517A-5 offers the possibillity of protecting the internal ROM against unauthorized access. This protection is implemented in the ROM-Mask.
Memory Organization 3.2 Data Memory The data memory space consists of an internal and an external memory space. The SAB 80C517A contains another 2 kByte of On-Chip RAM above the 256 Bytes internal RAM of the base type SAB 80C517. This RAM is called XRAM in this document. – External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16bit indirect addressing. For 8-bit addressing MOVX instructions in combination with registers R0 and R1 can be used.
Memory Organization 3.3 Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 81 special function registers include arithmetic registers, pointers, and registers that provide an interface between the CPU and the on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All special function registers are listed in table 3-1 and table 3-2.
Memory Organization Table 3-1, Special Function Register (cont´d) Address Register Contents after Reset Address Register Contents after Reset C0H C1H C2H C3H C4H C5H C6H C7H IRCON0 1) CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 00H 00H 00H 00H 00H 00H 00H 00H E0H E1H E2H E3H E4H E5H E6H E7H ACC 1) CTCON CML3 CMH3 CML4 CMH4 CML5 CMH5 00H 0X00 0000B 00H 00H 00H 00H 00H 00H C8H C9H CAH CBH CCH CDH CEH CFH T2CON 1) CC4EN CRCL CRCH TL2 TH2 CCL4 CCH4 00H 00H 00H 00H 00H 00H 00H 00H E8H E9H EAH EBH ECH EDH
Memory Organization Table 3-1, Special Function Register (cont´d) Block Symbol Name XRAM XPAGE Address Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP Page Address. Reg. for extended onchip 91H RAM XRAM Control Reg.
Memory Organization Table 3-1, Special Function Register Block Symbol Name Address Contents after Reset Compare/ CaptureUnit (CCU) (cont´d) CCL2 CCL3 CCL4 CMEM CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL COMSETL COMSETH COMCLRL COMCLRH SETMSK CLRMSK CTCON CTRELH CTRELL TH2 TL2 T2CON Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Comp./Capture Reg. 4, Low Byte Compare Enable Register Compare Reg. 0, High Byte Compare Reg.
Memory Organization Table 3-1, Special Function Register Block Symbol Name Address Contents after Reset Ports P0 P1 P2 P3 P4 P5 P6 P7 P8 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7, Analog/Digital Input Port 8, Analog/Digital Input, 4-bit 80H 1) 90H 1) A0H 1) B0H 1) E8H 1) F8H 1) FAH DBH DDH FFH FFH FFH FFH FFH FFH FFH – – Pow.
Memory Organization 3.4 Architecture for the XRAM The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the contents is undefined, while it remains unchanged during and after a reset or HW Power Down if the power supply is not turned off. The additional On-Chip RAM is logically located in the "external data memory" range at the upper end of the 64 KByte address range (F800H-FFFFH). It is possible to enable and disable (only by reset) the XRAM.
Memory Organization Accesses to XRAM using the Registers R0/R1 The 8051 architecture provides also instructions for access to external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX A, @ Ri (Read) MOVX @Ri, A (Write) In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as page register which selects pages of 256-Byte.
Memory Organization Figure 3-2 Write Page Address to Port 2 MOV P2, pageaddress will write the page address to Port 2 and XPAGE-Register. When external RAM is to be accessed in the XRAM address range (F800H - FFFFH) XRAM has to be disabled. When additional external RAM is to be addressed in an address range ≤ XRAM (F800H) XRAM may remain being enabled and there is no need to overwrite XPAGE by a second move.
Memory Organization Figure 3-3 Write Page Address to XPAGE The page address is only written to XPAGE-register. Port 2 is available for addresses or I/O-Data. See figure 3-4 to see what happens when Port 2 is used as I/O-Port.
Memory Organization Figure 3-4 Use of Port 2 as I/O-Port At a write to Port 2, XRAM address in XPAGE-register will be overwritten because of the concurrent write to Port 2 and XPAGE-register. So whenever XRAM is used and the XRAM address differs from the byte written to Port 2 latch it is absolutely nessesary to rewrite XPAGE with page address. Example: I/O-Data at Port 2 shall be 0AAH.
Memory Organization The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed from XPAGE and Ri is less than the XRAM address range, then an external access is performed. For the SAB 80C517A the contents of XPAGE must be greater or equal than F8H in order to use the XRAM. Of course, the XRAM must be enabled if it shall be used with MOVX @Ri instructions.
Memory Organization 3.4.2 Control of XRAM in the SAB 80C517A There are two control bits in register SYSCON which control the use and the bus operation during ^ XRAM). accesses to the additional On-Chip RAM in XDATA range ( = Special Function Register SYSCON Bit No. Addr. 0B1H MSB 7 6 5 4 3 2 – – – – – – 1 LSB 0 XMAP1 XMAP0 SYSCON Bit Function XMAP0 Global enable/disable bit for XRAM memory. XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled.
Memory Organization A hardware protection is done by an unsymetric latch at XMAP0-bit. A unintentional disabling of XRAM could be dangerous since indeterminate values could be read from external bus. To avoid this the XMAP-bit is forced to ’1’ only by reset. Additional during reset an internal capacitor is loaded. So the reset state is a disabled XRAM. Because of the load time of the capacitor XMAP0-bit once written to ’0’ (that is, discharging capacitor) cannot be set to ’1’ again by software.
Semiconductor Group 3 - 17 a)P0/P2→Bus a)P0/P2→Bus a)P0/P2→I/O (WR-Data only) b)RD/WR active b)RD/WR active b)RD/WR c)XRAM is used c) ext.memory inactive is used c)XRAM is used a)P0→Bus P2→I/O b)RD/WR active c)ext.memory is used a)P0→Bus a)P0/P2→I/O a)P0→Bus (WR-Data only) P2→I/O P2→I/O b)RD/WR active b)RD/WR active b)RD/WR inactive c)XRAM is used c)ext.memory c)XRAM is used is used a)P0→Bus P2→I/O b)RD/WR active c)ext.
System Reset 4 System Reset 4.1 Additional Hardware Power Down Mode in the SAB 80C517A The SAB 80C517A has an additional Power Down Mode which can be initiated by an external signal at a dedicated pin. This pin is labeled HWPD and is a floating input line (active low). This pin substitutes one of the VSS pins of the base types SAB 80C517 (PLCC84: Pin60; P-MQFP-100-2: Pin36).
System Reset Table 4-1, Status of all Pins During Hardware Power Down Mode Pins Status Voltage Range at Pin During HW-Power Down P0, P1, P2, P3, P4, Floating outputs / P5, P6, P7, P8 Disabled input function VSS ≤ VIN ≤ VCC EA active input VIN = VCC or VIN = VSS PE/SWD active input, Pull-up resistor disabled VIN = VCC or VIN = VSS during HW power down XTAL1 active output pin may not be driven XTAL2 disabled input function VSS ≤ VIN ≤VCC PSEN, ALE Floating outputs / Disabled input function (
System Reset The power down state is maintained while pin HWPD is held active. If HWPD goes to high level (inactive state) an automatic start up procedure is performed: – First the pins leave their floating condition and enter their default reset state as they had immediately before going to float state. – Both oscillators are enabled (only if OWE = high). While the on-chip oscillator (with pins XTAL1 and XTAL2) usually needs a longer time for start-up, if not externally driven (with crystal approx.
System Reset 4.2 Hardware Power Down Reset Timing Following figures are showing the timing diagrams for entering (figure 4-1) and leaving (figure 4-2) the Hardware Power Down Mode. If there is only a short signal at pin HWPD (i.e. HWPD is sampled active only once), then a complete internal reset is executed. Afterwards the normal program execution starts again (figure 4-3). Note: Delay time caused by internal logic is not included. The Reset pin overrides the Hardware Power Down function, i.e.
System Reset Figure 4-1 Timing Diagram of Entering Hardware Power Down Mode Semiconductor Group 4-5
System Reset Figure 4-2 Timing Diagram of Leaving Hardware Power Down Mode Semiconductor Group 4-6
System Reset Figure 4-3 Timing Diagram of Hardware Power Down Mode, HWPD-Pin is Active for only one cycle Semiconductor Group 4-7
System Reset 4.3 Fast internal Reset after Power-On The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 4-4 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family (like the SAB 80C517) enter their default reset state not before the on-chip oscillator starts.
System Reset After the on-chip oscillator finally has started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of 768 cycles of the RC oscillator in order to allow the oscillation of the on-chip oscillator to stabilize (figure 4-4, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog’s reset request is released (figure 4-4, III).
System Reset Figure 4-4 Power-On of the SAB 80C517A Semiconductor Group 4 - 10
On-Chip Peripheral Components 5 On-Chip Peripheral Components 5.1 Digital I/O Port Circuitry To realize the Hardware Power Down Mode with floating Port pins in the SAB 80C517A/83C517A 5 the standard port structure used in the 8051 Family is modified (figure 5-1). The FETs p4, p5 and n2 are added. During Hardware Power Down this FETs disconnect the port pins from internal logic.
On-Chip Peripheral Components P1 and p3 are not active during Hardware Power Down. P1 is activated only for two oscillator periods if a 0-to-1 transition is programmed to the port pin (not possible during HWPD). P3 is turned off during reset state (also HWPD). For detailled description of the port structure please refer to the SAB 80C517/80C537 User’s Manual.
On-Chip Peripheral Components 5.2 10-bit A/D-Converter In the SAB 80C517A is a new high performance / high speed 12-channel 10-bit A/D-Converter is implemented. Its successive approximation techniqe provides 7 µs conversion time (fOSC=16 MHz). The conversion principle is upward compatible to the one used in the SAB 80C517. The major components are shown in figure 5-1. The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages.
On-Chip Peripheral Components Figure 5-1 10-Bit A/D-Converter Semiconductor Group 5-4
On-Chip Peripheral Components Special Function Registers ADCON0, ADCON1 Bit No. MSB 7 6 5 4 3 2 1 LSB 0 Addr. 0D8H BD CLK ADEX BSY ADM MX2 MX1 MX0 Bit No. MSB 7 6 5 4 3 2 1 LSB 0 MX3 MX2 MX1 MX0 Addr. 0DCH ADCL ADCON0 ADCON1 These bits are not used in controlling A/D converter functions in the 80C517A Bit Function ADEX Internal / external start of conversion. When set, the external start of conversion by P6.0 / ADST is enabled. BSY Busy flag.
On-Chip Peripheral Components Special Function Register ADDATH, ADDATL Bit No. MSB 7 Addr. 0D9H msb Bit No. MSB 7 Addr. 0DAH 6 5 4 3 2 1 LSB 0 ADDATH 6 5 4 3 lsb 2 1 LSB 0 ADDATL These bits are not used for conversion result The reset value of ADDATH and ADDATL is 00H. The registers ADDATH (0D9H) and ADDATL (0DAH) contain the 10-bit conversion result. The data is read as two 8-bit bytes. Data is presented in left justified format (i.e.
On-Chip Peripheral Components A/D Converter Timing After a conversion has been started (by a write to ADDATL, external start by P6.0/ADST or in continous mode) the analog input voltage is sampled for 4 clock cycles. The analog source must be capable of charging the capacitor network of appr. 50 pF to full accuracy in this time. During this period the converter is susceptable to spikes and noise at the analog input, which may cause wrong codes at the digital outputs.
On-Chip Peripheral Components 5.3 Additional Compare Mode for the Concurrent Compare Unit The SAB 80C517A has an additional compare mode (compare mode 2) in the Compare/Capture Unit which can be used for the Concurrent Compare Output at P5. In this compare mode 2 the P5 pins are no longer general purpose I/O pins or under control of compare/capture register CC4, but under control of the new compare registers COMSET and COMCLR.
On-Chip Peripheral Components Figure 5-3 Compare Mode 2 (Port 5 only) Semiconductor Group 5-9
On-Chip Peripheral Components Special Function Register CC4EN Bit No. 0C9H MSB 7 6 5 4 3 2 COCOEN1 COCON2 COCON1 COCON0 COCOEN0 COCAH4 1 LSB 0 COCAL4 COM0 CC4EN Bit Function COCON2 COCON1 COCON0 Selects number of compare outputs at P5 (for compare modes 1 and 2); see table 2-2 COCAH4 COCAL4 Compare/capture mode for register CC4 and compare modes 1 and 2 at P5 Compare/capture at CC4 disabled Capture on falling/rising edge at pin P1.
On-Chip Peripheral Components Table 5-3, Configurations for Concurrent Compare Mode and Compare Mode 2 at P5 COCAH4 COCAL4 COCOEN1 COCOEN0 Function of CC4 Function of Compare Modes at P5 0 0 0 0 Compare / Capture disabled Compare / Capture disabled Disabled 0 0 1 0 0 0 1 1 Compare / Capture disabled Compare Mode 2 selected at P5 0 1 0 0 Disabled 1 1 0 Capture on falling/ rising edge at pin P1.
On-Chip Peripheral Components The following table 5-4 lists the SFR’s with their addresses and default values after reset which are used in compare mode 2: Table 5-4, Compare Mode 2, used SFR’s and their default Reset Value SFR Address Default Value after Reset COMSETL 0A1H 0A2H 00H COMSETH COMCLRL 00H 0A3H 0A4H COMCLRH SETMSK 00H 00H 0A5H 0A6H CLRMSK CTCON 00H 00H 0E1H 0C9H CC4EN 0X00 0000B 00H The compare registers COMSET and COMCLR have their dedicated interrupt vectors.
On-Chip Peripheral Components Extended Prescaler for Timer 2 The prescaler for Timer 2 has an extended range. This prescaler divides the input clock for Timer 2 when it is operated in timer mode. In addition to the ÷ 2 option there are now scale ratings of ÷ 4 and ÷ 8 available. The rate is selected by the control bits T2PS (T2CON.7) and T2PS1 (CTCON.7). Table 5-5 lists all available options. This prescaler must not be used when Timer 2 is operated in counter mode.
On-Chip Peripheral Components 5.4 New Baud Rate Generators for Serial Channel 0 and Serial Channel 1 5.4.1 Serial Channel 0 Baud Rate Generator The Serial Channel 0 has a new baud rate generator which provides greater flexibility and better resolution. It substitutes the 80C517’s baud rate generator at Serial Channel 0 which provides only 4.8 kBaud or 9.6 kBaud at 12 MHz crystal frequency.
On-Chip Peripheral Components Special Function Register S0RELH, S0RELL MSB 7 Bit No. 6 5 4 3 2 Addr. 0BAH msb MSB 7 Bit No. 1 LSB 0 6 5 4 3 2 1 Addr. 0AAH S0RELH LSB 0 lsb shaded areas are not used for programming the baudrate timer Bit Function S0RELH.0-1 Reload value. Upper two bits of the timer reload value. S0RELL.0-7 Reload value. Lower 8 bit of timer reload value. Reset value of S0RELL is 0D9H, S0RELH contains XXXX XXX11B.
On-Chip Peripheral Components Figure 5-5 shows a block diagram of the options available for baud rate generation of Serial Channel 0. It is a fully compatible superset of the functionality of the SAB 80C517. The new baud rate generator can be used in modes 1 and 3 of the Serial Channel 0. It is activated by setting bit BD (ADCON0.7). This also starts the baud rate timer. When Timer1 shall be used for baud rate generation, bit BD must be cleared. In any case, bit SMOD (PCON.
On-Chip Peripheral Components 5.4.2 Serial Channel 1 Baud Rate Generator A new baud rate generator for Serial Channel 1 now offers a wider range of selectable baud rates. Especially a baud rate of 1200 baud can be achieved now. The baud rate generator itself is identical with the one used for Serial Channel 0. It consists of a free running 10-bit timer with FOSC /2 input frequency. On overflow of this timer there is an automatic reload from the registers S1RELL (address 9DH) and S1RELH (address BBH).
On-Chip Peripheral Components Special Function Register SRELH, SRELL MSB 7 Bit No. 6 5 4 3 2 Addr. 0BBH msb MSB 7 Bit No. 1 LSB 0 6 5 4 3 2 1 Addr. 09DH S1RELH LSB 0 lsb shaded areas are not used for programming the baudrate timer Bit Function S1RELH.0-1 Reload value. Upper two bits of the timer reload value. S1RELL.0-7 Reload value. Lower 8 bit of timer reload value. Reset value of S1RELL is 00H, S1RELH contains XXXX XXX11B.
On-Chip Peripheral Components 5.5 Modified Oscillator Watchdog Unit The SAB 80C517A has a new oscillator watchdog unit that has an improved functionality with respect to the SAB 80C517’s oscillator watchdog. Use of the Oscillator Watchdog Unit The unit serves three functions: – Monitoring of the on-chip oscillator's function.
On-Chip Peripheral Components Detailled Description of the Oscillator Watchdog Unit Figure 5-7 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the onchip oscillator. The RC oscillator can be enabled/disabled by the control pin OWE . If it is disabled the complete unit has no function. Figure 5-7 Oscillator Watchdog Unit Special Function Register IP0 (Address 0A9H) Bit No.
On-Chip Peripheral Components The frequency coming from the RC oscillator is divided by 5 and compared to the on-chip oscillator’s frequency. If the frequency coming from the on-chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition (the oscillation at the on-chip oscillator could stop because of crystal damage etc.). In this case it switches the input of the internal clock system to the output of the RC oscillator.
Interrupt System 6 Interrupt System 6.1 Additional Interrupt for Compare Registers CM0 to CM7 There is an additional interrupt which is vectored to on a compare match in one of the eight comparators of the compare registers CM0 to CM7, when compare mode 1 is selected for the corresponding channel (assigned to Timer 2 by control bit CMSEL.x).
Interrupt System Figure 6-1 Interrupts of Compare Registers CM0-CM7 Assigned to Timer II Semiconductor Group 6-2
Interrupt System Special Function Register IRCON1 Bit No. MSB 7 0D1H ICMP7 6 5 4 3 2 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 1 LSB 0 ICMP1 ICMP0 IRCON1 Bit Function ICMPx Compare x interrupt request flag. Set by hardware when a compare match in compare mode 1 with compare register CMx occured (only, if compare function enabled for CMx). ICMPx must be cleared by software (CMSEL.x = 0 and CMEN.x = 1). The reset value of IRCON1 is 00H.
Interrupt System 6.2 Interrupt Structure This section summarizes the expanded interrupt structure of the SAB 80C517A which has 3 new interrupt vectors in addition to the 14 vectors of the SAB 80C517. Thus, 17 vectors are available now. The new interrupt sources are: 1. Request Flags ICMP0 to ICMP7: These eight request flags are set by compare matches in the compare registers CM0-7, if the compare function is enabled and compare mode 1 is selected for the corresponding register SCM0-7.
Interrupt System 3.1 Priority Level Structure The following tables show the SFR IEN2, the priority level grouping (table 6-1) and the priority within level (table 6-2). The principle of the priority level selection is identical to the SAB 80C517, i.e. a pair or triple can be programmed to one of four priority levels. Special Function Register IEN2 Bit No. 09AH MSB 7 – 6 5 4 3 2 1 LSB 0 – ECR ECS ECT ECMP – ES1 IEN2 Bit Function ES1 Enable serial interrupt of interface 1.
Interrupt System Table 6-1, Pairs and triplets of interrupt sources External Interrupt 0 Serial Channel 1 Interrupt A/D Converter Interrupt Timer 0 Interrupt – External Interrupt 2 External Interrupt 1 Match in CM0 - CM7 External Interrupt 3 Timer 1 Interrupt Compare Timer Overflow External Interrupt 4 Serial Channel 0 Interrupt Match in COMSET External Interrupt 5 Timer 2 Interrupt Match in COMCLR External Interrupt 6 Table 6-2, Priority within Level Interrupt Source High IE0 TF0 IE1 TF1
Device Specification 4 Device Specification High-Performance 8-Bit CMOS Single-Chip Microcontroller SAB 80C517A/83C517A-5 Preliminary SAB 83C517A-5 SAB 80C517A ● ● ● ● ● ● ● ● ● Microcontroller with factory mask-programmable ROM Microcontroller for external ROM SAB 80C517A/83C517A-5, up to 18 MHz operation 32 K × 8 ROM (SAB 83C517A-5 only, ROM-Protection available) 256 × 8 on-chip RAM 2 K × 8 on-chip RAM (XRAM) Superset of SAB 80C51 architecture: – 1 µs instruction cycle time at 12 MHz – 666 ns inst
Device Specification Ordering Information Type Ordering code Package SAB 80C517A-N18 Q67120-C583 P-LCC-84 SAB 80C517A-M18 TBD P-MRFP-100 SAB 83C517A-5N18 Q67120-C582 P-LCC-84 with mask-programmable ROM, 18 MHz SAB 80C517A-N18-T3 Q67120-C769 P-LCC-84 for external memory,18 MHz ext. temperature – 40 to 85 oC SAB 83C517A-5N18-T3 Q67120-C771 P-LCC-84 with mask-programmable ROM, 18 MHz ext. temperature – 40 to 85 oC SAB 83C517A-N18-T4 TBD P-LCC-84 for external memory, 18 MHz ext.
Device Specification Logic Symbol Semiconductor Group 7-3
Device Specification The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with one exception: Typ P-LCC-84, Pin 60 P-MQFP-100-2,Pin 36 SAB 80C517A SAB 80C517/80C537 HWPD N.C.
Device Specification Pin Configuration (P-MQFP-100-2) Semiconductor Group 7-5
Device Specification Pin Definitions and Functions Symbol Pin Number P-LCC-84 I/O *) Function P-MQFP-100-2 P4.0 – P4.7 1– 3, 5 – 9 64 - 66, 68 - 72 I/O Port 4 is a bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors.
Device Specification Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function I RESET A low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C517A. A small internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. P-LCC-84 P-MQFP-100-2 RESET 10 73 V AREF 11 78 Reference voltage for the A/D converter. V AGND 12 79 Reference ground for the A/D converter. P7.7 -P7.
Device Specification Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P3.0 - P3.7 21 - 28 I/O *) Function P-MQFP-100-2 90 - 97 I/O Port 3 is a bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pull-up resistors.
Device Specification Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P1.7 - P1.0 29 - 36 I/O *) Function P-MQFP-100-2 98 - 100, 1, 6 - 9 I/O Port 1 is a bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs.
Device Specification Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function P-LCC-84 P-MQFP-100-2 XTAL2 39 12 – XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL1 40 13 – XTAL1 Output of the inverting oscillator amplifier. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected.
Device Specification Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function P-LCC-84 P-MQFP-100-2 PSEN 49 22 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal program execution.
Device Specification Pin Definitions and Functions (cont’d) Symbol HWPD Pin Number I/O *) Function P-LCC-84 P-MQFP-100-2 60 36 I Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C517A. A low level for a longer period will force the part to Power Down Mode with the pins floating. (see table 7) 37 - 44 I/O Port 5 is a bidirectional I/O port with internal pullup resistors.
Device Specification Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P6.0 - P6.7 70 - 77 I/O *) Function P-MQFP-100-2 46 - 50, 54 - 56 I/O Port 6 is a bidirectional I/O port with internal pullup resistors. Port 6 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 6 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors.
Device Specification Pin Definitions and Functions (cont’d) Symbol Pin Number I/O *) Function P-LCC-84 P-MQFP-100-2 RO 82 61 O Reset Output This pin outputs the internally synchronized reset request signal. This signal may be generated by an external hardware reset, a watchdog timer reset or an oscillator watch-dog reset. The reset output is active low. VS S 37, 83 10, 62 – Circuit ground potential VCC 38, 84 11, 63 – Supply Terminal for all operating modes N.C.
Device Specification Figure 1 Block Diagram Semiconductor Group 7-15
Device Specification Functional Description The SAB 80C517A is based on 8051 architecture. It is a fully compatible member of the Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced SAB 80C517. The SAB 80C517A is therefore compatible with code written for the SAB 80C517. Having an 8-bit CPU with extensive facilities for bit-handling and binary BCD arithmetics the SAB 80C517A is optimized for control applications. With a 18 MHz crystal, 58 % of the instructions are executed in 666.
Device Specification Program Memory (’Code Space’) The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal ROM. The program memory can externally be expanded up to 64 Kbyte. Pin EA controls whether program fetches below address 8000H are done from internal or external memory. As a new feature the SAB 83C517A-5 offers the possibility of protecting the internal ROM against unauthorized access. This protection is implemented in the ROM-Mask.
Device Specification Data Memory (’Code Space’) The data memory space consists of an internal and an external memory space. The SAB 80C517A contains another 2 Kbyte on On-Chip RAM above the 256-bytes internal RAM of the base type SAB 80C517. This RAM is called XRAM in this document. External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16-bit indirect addressing. For 8-bit addressing MOVX instructions in combination with registers R0 and R1 can be used.
Device Specification Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM. Note: If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the cycle which the reset is detected at (MOVX is a 2-cycle instruction): Reset detection at cycle 1: The new value will not be written to XRAM. The old value is not affected.
Device Specification Special Function Register XPAGE Addr. 91H XPAGE The reset value of XPAGE is 00H. XPAGE can be set and read by software. The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed from XPAGE and Ri is less than the XRAM address range, then an external access is performed. For the SAB 80C517A the contents of XPAGE must be greater or equal than F8H in order to use the XRAM.
Device Specification Control of XRAM in the SAB 80C517A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On-Chip RAM (XRAM). Special Function Register SYSCON Addr. 0B1H — — — — — — XMAP1 XMAP0 SYSCON Bit Function XMAP0 Global enable/disable bit for XRAM memory. XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled. XMAP0 = 1: The access to XRAM is disabled.
Device Specification XMAP0 is hardware protected by an unsymmetric latch. An unintentional disabling of XRAM could be dangerous since indeterminate values would be read from external bus. To avoid this the XMAP-bit is forced to ’1’ only by reset. Additionally, during reset an internal capacitor is loaded. So after reset state XRAM is disabled. Because of the load time of the capacitor XMAP0-bit once written to ’0’ (that is, discharging capacitor) cannot be set to ’1’ again by software.
Semiconductor Group MOVX @Ri MOVX @DPTR 7-23 a) P0/P2➝BUS (WR -Data only) P2➝I/0 b) RD/WR active c) XRAM is used (WR -Data only) P2➝I/0 b) RD/WR inactive c) XRAM is used b) RD/WR active c) ext. memory is used b) RD/WR active c) ext. memory is used a) P0/P2➝BUS a) P0➝Bus P2➝I/0 b) RD/WR active c) XRAM is used b) RD/WR inactive c) XRAM is used P2➝I/0 (WR -Data only) a) P0➝Bus a) P0/P2➝BUS (WR -Data only) b) RD/WR active c) ext. memory is used b) RD/WR active c) ext.
Device Specification Multiple Datapointers As a functional enhancement to standard 8051 controllers, the SAB 80C517A contains eight 16-bit datapointers. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in special function register DPSEL (data pointer select, addr. 92H). Figure 3 illustrates the addressing mechanism.
Device Specification Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 81 special function registers include arithmetic registers, pointers, and registers that provide an interface between the CPU and the on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All special function registers are listed in table 1 and table 2.
Device Specification Table 2 Special Function Register (cont’d) Address Register Contents after Reset Address Register Contents after Reset B0H B1H B2H B3H B4H B5H B6H B7H P3 1) SYSCON reserved reserved reserved reserved reserved reserved 0FFH XXXX XX01B XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) D0H D1H D2H D3H D4H D5H D6H D7H PSW 1) IRCON1 CML0 CMH0 CML1 CMH1 CML2 CMH2 00H 00H 00H 00H 00H 00H 00H 00H B8H B9H BAH BBH BCH BDH BSH BFH IEN1 1) IP1 S0RELH S1RELH reserved reserved reserved reserved
Device Specification Table 2 Special Function Register (cont’d) Address Register Contents after Reset Address Register Contents after Reset F0H F1H F2H F3H F4H F5H F6H F7H B 1) reserved CML6 CMH6 CML7 CMH7 CMEN CMSEL 00H XXH 00H 00H 00H 00H 00H 00H F8H F9H FAH FBH FCH FDH FEH FFH P5 1) reserved P6 reserved reserved (IS0) (IS1) reserved 0FFH XXH 0FFH XXH XXH XXH XXH XXH 1) Bit-addressable special function registers X means that the value is indeterminate and the location is reserved 3) ( )...
Device Specification Table 3 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer 0E0H 1) 0F0H 1) 83H 82H 92H 0D0H 1) 81H 00H 00H 00H 00H XXXX X000B3) 00H 07H A/DConverter ADCON0 ADCON1 ADDATH ADDATL A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data
Device Specification Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset Compare/ CaptureUnit (CCU) Timer 2 CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 CCL2 CCL3 CCL4 CMEN CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL COMSETL COMSETH COMCLRL COMCLRH SETMSK Comp./Capture Enable Reg. Comp./Capture Enable 4 Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg.
Device Specification Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset Compare/ CaptureUnit (CCU), (cont’d) CLRMSK 0A6H 00H CTCON CTRELH CTRELL TH2 TL2 T2CON Mask Register, concerning COMCLR Com. Timer Control Reg. Com. Timer Rel. Reg., High Byte Com. Timer Rel. Reg.
Device Specification Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H 1) 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Watchdog IEN0 2) IEN1 2) IP0 2) IP1 2) WDTREL Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Regis
Device Specification A/D Converter In the SAB 80C517A a new high performance / high-speed 12-channel 10-bit A/D-Converter is implemented. Its successive approximation technique provides 7 µs con-version time (fOSC= 16 MHz). The conversion principle is upward compatible to the one used in the SAB 80C517. The main functional blocks are shown in figure 4. The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages.
Device Specification Figure 4 Block Diagram A/D Converter Semiconductor Group 7-33
Device Specification Compare/Capture Unit (CCU) The compare/capture unit is a complex timer/register array for applications that require high speed I/O pulse width modulation and more timer/counter capabilities. The CCU contains – one 16-bit timer/counter (timer2) with 2-bit prescaler, reload capability and a max. clock frequency of fOSC/12 (1 MHz with a 12 MHz crystal). – one 16-bit timer (compare timer) with 8-bit prescaler, reload capability and a max.
Device Specification Table 4 CCU Compare Configuration Assigned Timer Compare Register Compare Output Possible Modes Timer 2 CRCH/CRCL CC1H/CC1L CC2H/CC2L CC3H/CC3L CC4H/CC4L P1.0/INT3/CC0 P1.1/INT4/CC1 P1.2/INT5/CC2 P1.3/INT6/CC3 P1.4/INT2/CC4 Comp. mode 0, 1 + Reload Comp. mode 0, 1 Comp. mode 0, 1 Comp. mode 0, 1 Comp. mode 0, 1 CC4H/CC4L : CC4H/CC4L P5.0/CCM0 : P5.7/CCM7 Comp. mode 1 : Comp. mode 1 COMSETL/COMSETH P5.0/CCM0 : P5.7/CCM7 Comp. mode 2 : Comp. mode 2 P5.0/CCM0 : P5.
Device Specification Figure 5 Block Diagram of the Compare/Capture Unit Semiconductor Group 7-36
Device Specification Compare In compare mode, the 16-bit values stored in the dedicated compare registers are compared to the contents of the timer 2 register or the compare timer register. If the count value in the timer registers matches one of the stored value, an appropriate output signal is generated at the corresponding pin(s) and an interrupt is requested. Three compare modes are provided: Mode 0: Upon a match the output signal changes from low to high. It returns to low level at timer overflow.
Device Specification Reload of Timer 2 A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the 8-bit registers CRCL and CRCH. There are two modes from which to select: Mode 0: Reload is caused by a timer overflow (auto-reload). Mode 1: Reload is caused in response to a negative transition at pin T2EX (P1.5), which can also request an interrupt.
Device Specification Figure 6 Block Diagram of Timer 2 Semiconductor Group 7-39
Device Specification Figure 7 Block Diagram of the Compare Timer Figure 8 Compare-Mode 0 with Registers CM0 to CM7 Semiconductor Group 7-40
Device Specification Figure 9 Compare-Mode 2 (Port 5 only) Semiconductor Group 7-41
Device Specification Interrupt Structure The SAB 80C517A has 17 interrupt vectors with the following vector addresses and request flags. Table 5 Interrupt Sources and Vectors Interrupt Request Flags Interrupt Vector Address Interrupt Source IE0 TF0 IE1 TF1 RI0 + TI0 TF2 + EXF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 RI1/TI1 ICMP0 to ICMP7 0003H 000BH 0013H 001BH CTF ICS 009BH ICR 00ABH External interrupt 0 Timer 0 overflow External interrupt 1 Timer 1 overflow Serial channel 0 Timer 2 overflow/ext.
Device Specification Figure 10 Interrupt Structure of the SAB 80C517A Semiconductor Group 7-43
Device Specification Figure 10 Interrupt Structure of the SAB 80C517A (cont’d) Semiconductor Group 7-44
Device Specification Figure 10 Interrupt Structure of the SAB 80C517A (cont’d) Semiconductor Group 7-45
Device Specification Multiplication/Division Unit This on-chip arithmetic unit provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are integer operation. Operation Result Remainder Execution Time 32-bit/16-bit 32-bit 16-bit 6 t cy 1) 16-bit/16-bit 16-bit 16-bit 4 t cy 16-bit *16-bit 32-bit – 4 t cy 32-bit normalize – – 6 t cy 2) 32-bit shift left/right – – 6 t cy 2) 1) 2) 1 tcy = 1 µs @ 12 MHz oscillator frequency.
Device Specification Table 6 Performing a MDU-Calculation Operation 32 Bit/16 Bit 16 Bit/16 Bit 16 Bit * 16 Bit First Write MD0 MD1 MD2 MD3 MD4 MD5 D’endL D’end D’end D’endH D’orL D’orH MD0 MD1 D’endL D’endH MD0 MD4 M’andL M’orL MD4 D’orL MD1 M’andH MD5 D’orH MD5 M’orH MD0 MD1 MD2 MD3 MD4 MD5 QuoL Quo Quo QuoH RemL RemH MD0 MD1 QuoL QuoH MD0 MD1 PrL MD4 RemL MD2 MD5 RemH MD3 Last Write First Read Last Read PrH Table 7 Shift Operation with the MDU Operation Normalize, Shif
Device Specification with internal pull-up resistors. That means, when configured as inputs, ports 1 to 6 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. Port 0 and port 2 can be used to expand the program and data memory externally. During an access to external memory, port 0 emits the low-order address byte and reads/writes the data byte, while port 2 emits the high-order address byte.
Device Specification Power Saving Modes The SAB 80C517A provides – due to Siemens ACMOS technology – four modes in which power consumption can be significantly reduced. – The Slow Down Mode The controller keeps up the full operating functionality, but is driven with one eighth of its normal operating frequency. Slowing down the frequency remarkable reduces power consumption. – The Idle Mode The CPU is gated off from the oscillator, but all peripherals are still supplied with the clock and continue working.
Device Specification Requirements for Hardware Power Down Mode There is no dedicated pin to enable the Hardware Power Down Mode. Nevertheless for a correct function of the Hardware Power Down Mode the oscillator watchdog unit including its internal RC oscillator is needed. Therefore this unit must be enabled by pin OWE (OWE = high). However, the control pin PE/SWD has no control function in this mode. It enables and disables only the use of software controlled power saving modes.
Device Specification Power Down Mode The power down mode is entered by two consecutive instructions directly following each other. The first instruction has to set the flag PDE (power down enable) and must not set PDS (power down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will automatically be cleared after having been set. The instruction that sets bit PDS is the last instruction executed before going into power down mode.
Device Specification Table 8 Status of all pins during Idle Mode, Power Down Mode and Hardware Power Down Mode Pins Idle Mode Last instruction executed from internal ROM external ROM Power Down Mode Last instruction executed from internal ROM external ROM Hardware Power Down Status P0 Data float Data float P1 Data alt outputs Data alt outputs Data last outputs Data last outputs floating P2 Data Address Data Data output P3 Data alt outputs Data alt outputs Data Data outputs last o
Device Specification Table 8 Status of all pins during Idle Mode, Power Down Mode and Hardware Power Down Mode (cont’d) Pins Idle Mode Last instruction executed from internal ROM external ROM Power Down Mode Last instruction executed from internal ROM Status Voltage range at pin VSS ≤ VIN≤ VCC ALE floating outp. disabled input functions VAREF VAGND active supply pins VAGND ≤ VIN ≤ VCC OWE active input, must be high pull-up disabl.
Device Specification Serial Interfaces The SAB 80C517A has two serial interfaces. Both interfaces are full duplex and receive buffered. They are functionally identical with the serial interface of the SAB 8051 when working as asynchronous channels. Serial interface 0 additionally has a synchronous mode. Table 9 shows possible configurations and the according baud rates. Table 9 Baud Rate Generation Mode 8-Bit synchronous channel Baudrate Mode 0 f O SC =1 2 MHz 1MHz – fOSC = 16 MHz 1.
Device Specification Serial Interface 0 Serial Interface 0 can operate in 4 modes: Mode 0: Shift register mode: Serial data enters and exits through R × D0. T × D0 outputs the shift clock 8 data bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. Mode 1: 8-bit UART, variable baud rate: 10-bit are transmitted (through T × D0) or received (through R × D0): a start bit (0), 8 data bits (LSB first), and a stop bit (1).
Device Specification Serial Interface 1 Serial interface 1 can operate in two asynchronous modes: Mode A: 9-bit UART, variable baud rate. 11 bits are transmitted (through T × D1) or received (through R × D1): a start bit (0), 8 data bits (LSB first), a programmable 9th, and a stop bit (1). On transmission, the 9th data bit (TB81 in S1CON) can be assigned to the value of 0 or 1. For example, the parity bit (P in the PSW) could be moved into TB81 or a second stop bit by setting TB81 to 1.
Device Specification Watchdog Units The SAB 80C517A offers two enhanced fail safe mechanisms, which allow an automatic recovery from hardware failure or software upset: – programmable watchdog timer (WDT), variable from 512 µs up to appr. 1.1 s time-out period @12 MHz. Upward compatible to SAB 80515 watchdog.
Device Specification Oscillator Watchdog The unit serves three functions: – Monitoring of the on-chip oscillator’s function. The watchdog supervises the on-chip oscillator’s frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is forced into reset; if the failure condition disappears (i.e.
Device Specification Figure 12 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group 7-59
Device Specification Fast internal reset after power-on The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally members of the 8051 family (like the SAB 80C517) enter their default reset state not before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state.
Device Specification Absolute Maximum Ratings Ambient temperature under bias................................................................. – 40 to 110° C Storage temperature ................................................................................... – 65 to 150 oC Voltage on VCC pins with respect to ground (VSS) ...................................... – 0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS) ........................................ – 0.5 to VCC +0.
Device Specification DC Characteristics (cont’d) Parameter Symbol Limit Values min. Unit Test condition max. Output low voltage (ports 1, 2, 3, 4, 5, 6) VOL – 0.45 V IOL=1.6 mA1) Output low voltage (ports ALE, PSEN, RO) VOL1 – 0.45 V IOL=3.2 mA 1) Output high voltage (ports 1, 2, 3, 4, 5, 6) VOH 2.4 0.9 VCC – – V V IOH =–80 µA IOH =–10 µA Output high voltage (port 0 in external bus mode, ALE, PSEN, RO) VOH1 2.4 0.
Device Specification Notes for page 62: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and ports 1, 3, 4, 5 and 6. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V.
Device Specification A/D Converter Characteristics V CC = 5 V + 10 %, – 15 %; V SS = 0 V VAREF = VCC ± 5%; VAGND = VSS ± 0.2 V; 0 to 70 oC for the SAB 80C517A/83C517A-5 TA= T A = – 40 to 85 o C for the SAB 80C517A-T3/83C517A-5-T3 T A = – 40 to 110 oC for the SAB 80C517A-T4/83C517A-5-T4 Parameter Symbol Limit values min. Analog input capacitance CI Unit typ. max. 25 70 pF Test condition Sample time (inc. load time) TS 4 t CY1) µs 2) Conversion time (inc.
Device Specification AC Characteristics V CC = 5 V + 10 %, – 15 %; V SS = 0 V TA= 0 to 70 oC for the SAB 80C517A/83C517A-5 T A = – 40 to 85 oC for the SAB 80C517A-T3/83C517A-5-T3 T A = – 40 to110 o C for the SAB 80C517A-T4/83C517A-5-T4 (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Parameter Symbol Limit values 18 MHz clock min. Unit Variable clock 1/t CLCL = 3.5 MHz to 18 MHz max. min. max.
Device Specification AC Characteristics (cont’d) Parameter Symbol Limit values 18 MHz clock min. Unit Variable clock 1/t CLCL = 3.5 MHz to 18 MHz max. min. max.
Device Specification t LHLL ALE t AVLL t PLPH t LLPL t LLIV t PLIV PSEN t AZPL t PXAV t LLAX t PXIZ t PXIX Port 0 A0 - A7 Instr.
Device Specification t WHLH ALE PSEN t LLWL t WLWH WR t QVWX t AVLL t WHQX t LLAX2 Port 0 A0 - A7 from Ri or DPL t QVWH Data OUT A0 - A7 from PCL Instr.IN t AVWL Port 2 P2.0 - P2.
Device Specification AC Characteristics (cont’d) Parameter Symbol Limit values Unit Variable clock Frequ. = 3.5 MHz to 18 MHz min. max. External Clock Drive Oscillator period tCLCL 55.6 285 ns High time tCHCX 20 tCLCL-tCHCX ns Low time tCLCX 20 tCLCL-tCHCX ns Rise time tCLCH – 20 ns Fall time tCHCL – 20 ns Oscillator frequency 1/tCLC 3.
Device Specification AC Characteristics (cont’d) Parameter Symbol Limit values 18 MHz clock min. max. Unit Variable clock 1/t CLCL = 3.5 MHz to 18 MHz min. max.
Device Specification ROM Verification Characteristics T A = 25°C ± 5°C; V CC = 5 V ± 10%; V SS = 0 V Parameter Symbol Limit values min. Unit max.
Device Specification ROM Verification Mode 2 (New Verify Mode for Protected and not Protected ROM) ROM Verification Mode 2 Semiconductor Group 7-72
Device Specification Application Circuitry for Verifying the Internal ROM Semiconductor Group 7-73
Device Specification AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’. AC Testing: Input, Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V OH/V OL level occurs. IOL/IOH ≥ ± 20 mA.
Device Specification Package Outlines Plastic Package, P-LCC-84 – SMD (Plastic Leaded Chip-Carrier) Dimensions in mm Plastic Package, P-MQFP-100-2 – SMD (Plastic Metric Rectangular Flat Package) Dimensions in mm SMD = Surface Mounted Device Semiconductor Group 7-75
