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Edition 04.97 This edition was realized using the software system FrameMaker. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
C501 User’s Manual Revision History : 04.97 Previous Releases : 02.96, 08.94, 08.93 (Original Version) Page (previous version) Page (new version) general Subjects (changes since last revision) C501G-1E OTP version included (new chapter 9, AC/DC characteristics now in chapter 10) Chapter 1 Chapter 1 1-2 3-4 to 3-6 4-2 6-10 6-15 follo. 6-23 follo. 6-30 follo.
C501 Table of Contents Page 1 1.1 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 2 2.1 2.2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CPU . . . . . . . . . . . .
C501 Table of Contents Page 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.4 6.3.5 6.3.6 Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Auto-Reload (Up or Down Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C501 Table of Contents Page 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 DC Characteristics for C501-L / C501-1R . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 DC Characteristics for C501-1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction C501 1 Introduction The C501-L, C501-1R, and C501-1E described in this document are compatible (also pincompatible) with the 80C52 and can be used in typical 80C52 applications. The C501-1R contains a non-volatile 8K×8 read-only program memory, a volatile 256×8 read/write data memory, four ports, three 16-bit timers/counters, a seven source, two priority level interrupt structure and a serial port. The C501-L is identical, except that it lacks the program memory on chip.
Introduction C501 Listed below is a summary of the main features of the C501: • • • • • • • • • • • • • Fully compatible to standard 8051 microcontroller Versions for 12/24/40 MHz operating frequency Program memory : completely external (C501-L) 8K × 8 ROM (C501-1R) 8K × 8 OTP memory (C501-1E) 256 × 8 RAM Four 8-bit ports Three 16-bit timers / counters (timer 2 with up/down counter feature) USART Six interrupt sources, two priority levels Power saving modes Quick Pulse programming algorithm (C501-1E only
Introduction C501 1.1 Pin Configuration 6 P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 5 4 3 2 7 8 9 10 11 12 13 14 15 16 17 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 N.C VCC This section shows the pin configuration of the C501 in the P-LCC-44, P-DIP-40, and P-MQFP-44 packages. 1 44 43 42 41 40 C501 39 38 37 36 35 34 33 32 31 30 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.
Introduction C501 T2/P1.0 1 40 VCC T2EX/P1.1 2 39 P0.0/AD0 P1.2 3 38 P0.1/AD1 P1.3 4 37 P0.2/AD2 P1.4 5 36 P0.3/AD3 P1.5 6 35 P0.4/AD4 P1.6 7 34 P0.5/AD5 P1.7 8 33 P0.6/AD6 RESET 9 32 P0.7/AD7 31 EA/VPP RxD/P3.0 10 C501 TxD/P3.1 11 30 ALE/PROG INT0/P3.2 12 29 PSEN INT1/P3.3 13 28 P2.7/A15 T0/P3.4 14 27 P2.6/A14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 16 25 P2.4/A12 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 Introduction C501 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C501 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC N.C. P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 Figure 1-5 Pin Configuration P-MQFP-44 Package (top view) Semiconductor Group 1-5 P2.4/A12 P2.3/A11 P2.
Introduction C501 1.2 Pin Definitions and Functions This section describes all external signals of the C501 with its function. Table 1-1 Pin Definitions and Functions Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 P1.0 – P1.7 2–9 2 3 1–8 40–44, 1–3, 1 2 40 41 I/O *) I = Input O = Output Semiconductor Group 1-6 Port 1 is a quasi-bidirectional I/O port with internal pull-up resistors.
Introduction C501 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 P3.0 – P3.7 11, 13–19 10–17 5, 7–13 11 10 5 13 11 7 14 12 8 15 13 9 16 17 18 14 15 16 10 11 12 19 17 13 I/O *) I = Input O = Output Semiconductor Group 1-7 Port 3 is a quasi-bidirectional I/O port with internal pull-up resistors.
Introduction C501 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 XTAL2 20 18 14 – XTAL2 Output of the inverting oscillator amplifier. XTAL1 21 19 15 – XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected.
Introduction C501 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 PSEN 32 29 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution.
Introduction C501 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 P0.0 – P0.7 43–36 39–32 37–30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory.
Fundamental Structure C501 2 Fundamental Structure The C501 is fully compatible to the standard 8051 microcontroller family. It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational characteristics of the 8051 microcontroller family, the C501 incorporates some enhancements in the timer 2 and fail save mechanism unit. Figure 2-6 shows a block diagram of the C501.
Fundamental Structure C501 2.1 CPU The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 12 MHz crystal, 58% of the instructions execute in 1.0 µs (24 MHz : 500 ns, 40 MHz : 300 ns).
Fundamental Structure C501 Special Function Register PSW (Address D0H) Reset Value : 00H Bit No. MSB D0H LSB D7H D6H D5H D4H D3H D2H D1H D0H CY AC F0 RS1 RS0 OV F1 P Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks.
Fundamental Structure C501 2.2 CPU Timing A machine cycle of the C501 consists of 6 states (12 oscillator periods). Each state is devided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods.
Fundamental Structure C501 Figure 2-7 Fetch Execute Sequence Semiconductor Group 2-5
Memory Organization C501 3 Memory Organization The C501 CPU manipulates operands in the following four address spaces: – – – – up to 64 Kbyte of internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C501.
Memory Organization C501 3.1 Program Memory, “Code Space” The C501-1R/-1E has 8 Kbytes of read-only/OTP program memory, while the C501-L has no internal program memory. The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C501 executes out of internal program memory unless the address exceeds 1FFFH. Locations 2000H through FFFFH are then fetched from the external program memory.
Memory Organization C501 3.4 Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 27 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in table 3-1 and table 3-2.
Memory Organization C501 Table 3-2 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL PSW SP Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer E0H 1) F0H 1) 83H 82H D0H 1) 81H 00H 00H 00H 00H 00H 07H Interrupt System IE IP Interrupt Enable Register Interrupt Priority Register A8H1) B8H 1) 0X000000B 3) XX000000B 3) Ports P0 P1 P2 P3 Port 0 Port 1 Port 2 Port 3 80H 1)
Memory Organization C501 Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H2) P0 FFH .7 .6 .5 .4 .3 .2 .1 .0 81H SP .7 .6 .5 .4 .3 .2 .1 .0 82H DPL 07H 00H .7 .6 .5 .4 .3 .2 .1 .0 83H DPH .7 .6 .5 .4 .3 .2 .1 .
Memory Organization C501 Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D0H2) PSW E0H2) ACC F0H2) B 00H 00H CY AC F0 RS1 RS0 OV F1 P .7 .6 .5 .4 .3 .2 .1 .0 00H .7 .6 .5 .4 .3 .2 .1 .
External Bus Interface C501 4 External Bus Interface The C501 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe.
External Bus Interface C501 a) One Machine Cycle S1 S2 S3 S4 S5 One Machine Cycle S6 S1 S2 S3 S4 S5 S6 ALE PSEN (A) without MOVX RD PCH OUT P2 P0 PCL OUT INST. IN PCH OUT INST. IN PCL OUT valid b) PCH OUT INST. IN PCL OUT PCL OUT valid S2 S3 S4 S5 INST. IN PCL OUT PCL OUT valid One Machine Cycle S1 PCH OUT INST. IN PCL OUT PCL OUT valid One Machine Cycle S6 S1 S2 S3 S4 S5 S6 ALE PSEN (B) with MOVX RD PCH OUT P2 P0 INST. IN PCL OUT DPH OUT OR P2 OUT INST.
External Bus Interface C501 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated.
External Bus Interface C501 4.2 PSEN, Program Store Enable The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD.
External Bus Interface C501 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too (not true for the C509-l, because it lacks internal program memory). Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
System Reset C501 5 System Reset 5.1 Hardware Reset The hardware reset function incorporated in the C501 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated. The RESET input is an active high input.
System Reset C501 5.2 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e.
On-Chip Peripheral Components C501 6 On-Chip Peripheral Components I/O Ports The C501 has four 8-bit I/O portst. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input.
On-Chip Peripheral Components C501 Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the 4 I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a “write-to-latch” signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a “read-latch” signal from the CPU.
On-Chip Peripheral Components C501 Port 1, 2 and 3 output drivers have internal pullup FET’s (see figure 6-5). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-5: Q=0), which turns off the output driver FET n1. Then, for ports 1, 2 and 3, the pin is pulled high by the internal pullups, but can be pulled low by an external source.
On-Chip Peripheral Components C501 In fact, the pullups mentioned before and included in figure 6-5 are pullup arrangements as shown in figure 6-6. One n-channel pulldown FET and three pullup FETs are used: VCC Delay = 1 State =1 <_ 1 p1 p2 p3 Port Pin n1 Q VSS Input Data (Read Pin) =1 =1 MCS03230 Figure 6-6 Output Driver Circuit of Ports 1 to 5 and 7 – The pulldown FET n1 is of n-channel type.
On-Chip Peripheral Components C501 The described activating and deactivating of the four different transistors results in four states which can be: – – – – input low state (IL), p2 active only input high state (IH) = steady output high state (SOH), p2 and p3 active forced output high state (FOH), p1, p2 and p3 active output low state (OL), n1 active If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will switch to IH state.
On-Chip Peripheral Components C501 Port 0, in contrast to ports 1, 2 and 3, is considered as “true” bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-7) is used only when the port is emitting 1 s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines.
On-Chip Peripheral Components C501 6.1.1.1 Port 0 and Port 2 used as Address/Data Bus As shown in figure 6-7 and below in figure 6-8, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally.
On-Chip Peripheral Components C501 6.1.2 Alternate Functions The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-4. Figure 6-9 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open.
On-Chip Peripheral Components C501 Ports 1 and 3 are provided for several alternate functions, as listed in table 6-4: Table 6-4 Alternate Functions of Port 1 and 3 Port Pin Alternate Function P1.0 P1.1 P3.0 T2 T2EX RxD P3.1 TxD P3.2 P3.3 P3.4 P3.5 P3.6 P3.
On-Chip Peripheral Components C501 6.1.3 Port Handling 6.1.3.1 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1).
On-Chip Peripheral Components C501 6.1.3.2 Port Loading and Interfacing The output buffers of ports 1, 2 and 3 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be looked up in the C501 DC characteristics in chapter 10. The corresponding parameters are VOL and VOH. The same applies to port 0 output buffers. They do, however, require external pullups to drive floating inputs, except when being used as the address/data bus.
On-Chip Peripheral Components C501 Table 6-5 Read-Modify-Write"- Instructions Instruction Function ANL Logic AND; e.g. ANL P1, A ORL Logic OR; e.g. ORL P2, A XRL Logic exclusive OR; e.g. XRL P3, A JBC Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL CPL Complement bit; e.g. CPL P3.0 INC Increment byte; e.g. INC P1 DEC Decrement byte; e.g. DEC P1 DJNZ Decrement and jump if not zero; e.g. DJNZ P3, LABEL MOV Px.y,C Move carry bit to bit y of port x CLR Px.
On-Chip Peripheral Components C501 6.2 Timers/Counters The C501 contains three 16-bit timers/counters, timer 0, 1, and 2, which are useful in many applications for timing and counting. In “timer” function, the timer register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the counter rate is 1/12 of the oscillator frequency.
On-Chip Peripheral Components C501 6.2.1 Timer/Counter 0 and 1 Timer / counter 0 and 1 of the C501 are fully compatible with timer / counter 0 and 1 of the 80C51 and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; Timer/ counter 1 in this mode holds its count.
On-Chip Peripheral Components C501 6.2.1.1 Timer/Counter 0 and 1 Registers Totally six special function registers control the timer/counter 0 and 1 operation : – TL0/TH0 and TL1/TH1 - counter registers, low and high part – TCON and TMOD - control and mode select registers Special Function Register TL0 (Address 8AH) Special Function Register TH0 (Address 8CH) Special Function Register TL1 (Address 8BH) Special Function Register TH1 (Address 8DH) Bit No. MSB 7 6 5 4 3 2 1 LSB 0 8AH .7 .6 .5 .
On-Chip Peripheral Components C501 Special Function Register TCON (Address 88H) Bit No. 88H MSB 7 Reset Value : 00H LSB 0 6 5 4 3 2 1 8FH 8EH 8DH 8CH 8BH 8AH 89H 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON The shaded bits are not used for controlling timer/counter 0 and 1. Bit Function TR0 Timer 0 run control bit Set/cleared by software to turn timer/counter 0 ON/OFF. TF0 Timer 0 overflow flag Set by hardware on timer/counter overflow.
On-Chip Peripheral Components C501 Special Function Register TMOD (Address 89H) Bit No. MSB 7 89H Gate 6 5 4 C/T M1 M0 Reset Value : 00H 3 Timer 1 Control Gate 2 1 C/T M1 LSB 0 M0 TMOD Timer 0 Control Bit Function GATE Gating control When set, timer/counter “x” is enabled only while “INT x” pin is high and “TRx” control bit is set. When cleared timer “x” is enabled whenever “TRx” control bit is set.
On-Chip Peripheral Components C501 6.2.1.2 Mode 0 Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by32 prescaler. Figure 6-11 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt.
On-Chip Peripheral Components C501 6.2.1.3 Mode 1 Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure 6-12. OSC ÷ 12 C/T = 0 C/T = 1 P3.4/T0 Control Gate TR0 =1 & <_ 1 P3.
On-Chip Peripheral Components C501 6.2.1.4 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 6-13. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.
On-Chip Peripheral Components C501 6.2.1.5 Mode 3 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperate counters. The logic for mode 3 on timer 0 is shown in figure 6-14. TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1.
On-Chip Peripheral Components C501 6.2.2 Timer/Counter 2 Timer 2 is a 16-bit timer / counter which can operate as timer or counter.
On-Chip Peripheral Components C501 6.2.2.1 Timer 2 Registers Totally six special function registers control the timer/counter 2 operation : – TL2/TH2 and RC2L/RC2H - counter and reload/capture registers, low and high part – T2CON and T2MOD - control and mode select registers Special Function Register TL2 (Address CCH) Special Function Register TH2 (Address CDH) Special Function Register RC2L (Address CAH) Special Function Register RC2H (Address CBH) Bit No.
On-Chip Peripheral Components C501 Special Function Register T2CON (Address C8H) Bit No. MSB CFH C8H TF2 CEH EXF2 CDH RCLK CCH CBH TCLK EXEN2 Reset Value : 00H CAH TR2 C9H LSB C8H C/T2 CP/RL2 T2CON Bit Function TF2 Timer 2 Overflow Flag. Set by a timer 2 overflow. Must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. EXF2 Timer 2 External Flag. Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
On-Chip Peripheral Components C501 Special Function Register T2MOD (Address C9H) Bit No. C9H MSB 7 6 – – 5 – 4 – 3 – Reset Value : XXXXXXX0B 2 – 1 – LSB 0 DCEN T2MOD The shaded bits are not used for controlling timer 2. Bit Function – Not implemented, reserved for future use. DCEN Down Counter Enable When set, this bit allows timer 2 to be configured as an up/down counter.
On-Chip Peripheral Components C501 6.2.2.2 Auto-Reload (Up or Down Counter) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by a bit named DCEN (Down Counter Enable, SFR T2MOD, 0C9H). When DCEN is set, timer 2 can count up or down depending on the value of pin T2EX (P1.1). Figure 6-15 shows timer 2 automatically counting up when DCEN = 0. In this mode there are two options selectable by bit EXEN2 in SFR T2CON.
On-Chip Peripheral Components C501 Figure 6-16 Timer 2 Auto-Reload Mode (DCEN = 1) A logic 1 at T2EX makes timer 2 count up. The timer will overflow at FFFF H and set the TF2 bit. This overflow also causes the 16-bit value in RC2H and RC2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes timer 2 count down. Now the timer underflows when TH2 and TL2 equal the values stored in RC2H and RC2L.
On-Chip Peripheral Components C501 6.2.2.3 Capture In the capture mode there are two options selected by bit EXEN2 in SFR T2CON. If EXEN2 = 0, timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in SFR T2CON. This bit can be used to generate an interrupt. If EXEN2 = 1, timer 2 still does the above, but with added feature that a 1-to-0 transition at external input T2EX causes the current value in TH2 and TL2 to be captured into RC2H and RC2L, respectively.
On-Chip Peripheral Components C501 6.3 Serial Interface The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receivebuffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. (However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost).
On-Chip Peripheral Components C501 6.3.1 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows.
On-Chip Peripheral Components C501 Special Function Register SCON (Address 98H) Special Function Register SBUF (Address 99H) Bit No.
On-Chip Peripheral Components C501 6.3.3 Baud Rates Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. For clarification some terms regarding the difference between “baud rate clock” and “baud rate” should be mentioned. The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization.
On-Chip Peripheral Components C501 6.3.3.1 Using Timer 1 to Generate Baud Rates When timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows: Modes 1,3 baud rate = 2SMOD/32×(timer 1 overflow rate) The timer 1 interrupt should be disabled in this application. The timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes.
On-Chip Peripheral Components C501 6.3.3.2 Using Timer 2 to Generate Baud Rates Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note then the baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts timer 2 into its baud rate generator mode, as shown in figure 6-18.
On-Chip Peripheral Components C501 The timer can be configured for either “timer” or “counter” operation: In the most typical applications, it is configured for “timer” operation (C/T2 = 0). “Timer” operation is a little different for timer 2 when it’s being used as a baud rate generator. Normally, as a timer it would increment every machine cycle (thus at fOSC/12). As a baud rate generator, however, it increments every state time (fOSC/2).
On-Chip Peripheral Components C501 6.3.4 Details about Mode 0 Serial data enters and exists through RxD. TxD outputs the shift clock. 8 data bits are transmitted/ received: (LSB first). The baud rate is fixed at fOSC/12. Figure 6-19 shows a simplyfied functional diagram of the serial port in mode 0. The associated timing is illustrated in figure 6-20. Transmission is initiated by any instruction that uses SBUF as a destination register.
On-Chip Peripheral Components C501 Internal Bus 1 Write to SBUF S Q & SBUF CLK Shift D Zero Detector Start Baud Rate S6 Clock Shift TX Control TX Clock TI RI Start Receive RX Control RX Clock 1 1 1 1 1 1 1 0 Shift Input Shift Register Shift Load SBUF SBUF Read SBUF Internal Bus MCS02101 Figure 6-19 Serial Interface, Mode 0, Functional Diagram Semiconductor Group <_ 1 Shift Clock & RI Send <_ 1 Serial Port Interrupt REN RXD P3.0 Alt. Output Function 6-37 RXD P3.0 Alt.
Semiconductor Group S6P2 Write to SBUF Figure 6-20 Serial Interface, Mode 0, Timing Diagram 6-38 TXD (Shift Clock) RXD (Data In) Write to SCON (Clear RI) D0 S3P1 S6P1 D0 S5P D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 MCT02102 Transmit Shift Receive RI TI TXD (Shift Clock) RXD (Data Out) Shift Send ALE SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 On-Chip Peripheral Components C5
On-Chip Peripheral Components C501 6.3.5 Details about Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. The baud rate is determined either by the timer 1 overflow rate, or the timer 2 overflow rate, or both (one for transmit and the other for receive). Figure 6-21 shows a simplified functional diagram of the serial port in mode 1.
On-Chip Peripheral Components C501 Internal Bus 1 Write to SBUF S Q & SBUF D CLK Zero Detector Shift Start Data TX Control ÷ 16 TX Clock Baud Rate Clock TI Send RI Load SBUF <_ 1 Serial Port Interrupt ÷ 16 Sample 1-to-0 Transition Detector RX Start RX Control 1FFH Shift Bit Detector Input Shift Register (9Bits) RXD Shift Load SBUF SBUF Read SBUF Internal Bus MCS02103 Figure 6-21 Serial Interface, Mode 1, Functional Diagram Semiconductor Group 6-40 <_ 1 TXD
Semiconductor Group TI TXD Shift Data Send Figure 6-22 Serial Interface, Mode 1, Timing Diagram 6-41 Receive RI Shift Bit Detector Sample Times Start Bit S1P1 D1 Start Bit ÷ 16 Reset D0 D0 D2 D1 D3 D2 D4 D3 D5 D4 D6 D5 D7 D6 D7 Stop Bit MCT02104 Stop Bit Transmit RXD RX Clock Write to SBUF TX Clock On-Chip Peripheral Components C501
On-Chip Peripheral Components C501 6.3.6 Details about Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in mode 2 (When bit SMOD in SFR PCON (87H) is set, the baud rate is fOSC/32).
On-Chip Peripheral Components C501 Internal Bus TB8 Write to SBUF S Q & SBUF D CLK Zero Detector Start ÷ 16 Stop Bit Shift Generation TX Control TX Clock Baud Rate Clock Data TI Send RI Load SBUF <_ 1 Serial Port Interrupt ÷ 16 Sample 1-to-0 Transition Detector RX Clock Start RX Control 1FF Bit Detector Shift Input Shift Register (9Bits) RXD Shift Load SBUF SBUF Read SBUF Internal Bus MCS02105 Figure 6-23 Serial Interface, Mode 2 and 3, Functional Diagram Semiconductor Group 6-43
Semiconductor Group Figure 6-24 Serial Interface, Mode 2 and 3, Timing Diagram 6-44 Receive RI Shift Sample Times Bit Detector ÷ 16 Reset Start Bit Start Bit RX Clock D0 Mode 2 : S6P1 Mode 3 : S1P1 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 TB8 RB8 Stop Bit MCT02587 Stop Bit Transmit RX Stop Bit Gen.
Interrupt System C501 7 Interrupt System The C501 provides 6 interrupt sources with two priority levels. Four interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2 and serial interface), and two interrupts may be triggered externally (P3.2/INT0 and P3.3/INT1). This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers.
Interrupt System C501 7.1 Interrupt Registers 7.1.1 Interrupt Enable Register Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable register IE (interrupt enable) or T2CON. This register also contains the global disable bit (EA), which can be cleared to disable all interrupts at once. Generally, after reset all interrupt enable bits are set to 0. That means that the corresponding interrupts are disabled.
Interrupt System C501 Special Function Register T2CON (Address C8H) Bit No. MSB CFH C8H TF2 CEH EXF2 CDH RCLK CCH CBH TCLK EXEN2 Reset Value : 00H CAH TR2 C9H LSB C8H C/T2 CP/RL2 T2CON The shaded bits are not used for interrupt enable control. Bit Function EXEN2 Timer 2 External Enable. When set, allows a capture or reload to occur as a result of a negative transition on pin T2EX (P1.1) if timer 2 is not being used to clock the serial port.
Interrupt System C501 7.1.2 Interrupt Request / Control Flags The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative transition-activated, depending on bits IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is generated, the flag that generated this interrupt is cleared by the hardware when the service routine is vectored too, but only if the interrupt was transition-activated.
Interrupt System C501 The timer 2 interrupt is generated by the logical OR of bit TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared by software. The serial port interrupt is generated by a logical OR of flag RI and TI in SFR SCON.
Interrupt System C501 7.1.3 Interrupt Priority Register Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in the SFR IP (Interrupt Priority, 0: low priority, 1: high priority). Special Function Register IP (Address B8H) Bit No. B8H MSB 7 – Reset Value : XX000000B 6 5 4 3 2 1 – PT2 PS PT1 PX1 PT0 The shaded bits are not used for interrupt control. Bit Function – Not implemented. Reserved for future use.
Interrupt System C501 7.2 Interrupt Priority Level Structure A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced.
Interrupt System C501 7.3 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1.
Interrupt System C501 Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7-26 then, in accordance with the above rules, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed. Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine.
Interrupt System C501 7.4 External Interrupts The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition activated by setting or clearing bit IT0, respectively in register TCON. If ITx = 0 (x = 0 or 1), external interrupt x is triggered by a detected low level at the INTx pin. If ITx = 1, external interrupt x is negative edge-triggered.
Interrupt System C501 7.5 Interrupt Response Time If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be next instruction to be executed. The call itself takes two cycles.
Power Saving Modes C501 8 Power Saving Modes The C501 provides two basic power saving modes : – – Idle mode Power down mode. 8.1 Power Saving Mode Control Register The two power saving modes are controlled by bits which are located in the special function registers PCON. The SFR PCON is located at SFR address 87H. The bits PDE and IDLE in SFR PCON select the power down mode or the idle mode, respectively. If the power down mode and the idle mode are set at the same time, power down takes precedence.
Power Saving Modes C501 8.2 Idle Mode In the idle mode the oscillator of the C501 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, and all timers are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode.
Power Saving Modes C501 8.3 Power Down Mode In the power down mode, the on-chip oscillator is stopped. Therefore all functions are stopped; only the contents of the on-chip RAM and the SFR’s are maintained. The port pins controlled by their port latches output the values that are held by their SFR’s. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power-down mode.
Power Saving Modes C501 8.4 State of Pins in Software Initiated Power Saving Modes In the idle mode and in the power down mode the port pins of the C501 have a well defined status which is listed in the following table 8-10. This state of some pins also depends on the location of the code memory (internal or external).
OTP Memory Operation C501 9 OTP Memory Operation of the C501-1E The C501-1E is the OTP version of the C501-1R ROM version microcontroller. Its functionality is fully compatible with the C501-1R functionality. This chapter describes in detail the programming features of the C501-1E. 9.1 Programming Modes The C501-1E is programmed by usng a modified Quick-Pulse Programming TM 1) algorithm.
OTP Memory Operation C501 9.2 Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in figure 9-28. Note that the C501-1E is running with a 4 to 6 MHz oscillator The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. +5 V A0 - A7 Port 1 C501-1E 1 RESET 1 1 P3.6 P3.7 VCC Programming Data Port 0 EA/VPP +12.75 V 25 x 100 µs Low Pulses 0 ALE/PROG XTAL2 PSEN 4 - 6 MHz P2.7 1 P2.
OTP Memory Operation C501 Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoots. 9.3 Encryption Table The encryption table feature of the C501-1E is a feature that protects the program code in the OTP memory from being easily read by anyone other than the programmer.
OTP Memory Operation C501 9.5 OTP Memory Verification If security bit 2 has not been programmed, the on-chip OTP program memory can be read out for program verification. The address of the OTP program memory locations to be read is applied to ports 1 and 2 as shown in figure 9-30. The other pins are held at the “Verify code data“ levels indicated in table 9-11. The contents of the address location will be emitted on port 0. External pullups are required on port 0 for this operation.
Device Specifications C501 10 Device Specifications 10.1 Absolute Maximum Ratings Ambient temperature under bias (TA) ......................................................... Storage temperature (Tstg) .......................................................................... Voltage on VCC pins with respect to ground (VSS) ....................................... Voltage on any pin with respect to ground ( VSS) ......................................... Input current on any pin during overload condition.
Device Specifications C501 10.2 DC Characteristics for C501-L / C501-1R VCC = 5 V + 10 %, – 15 %; VSS = 0 V; Parameter TA = 0 °C to 70 °C for the SAB-C501 TA = – 40 °C to 85 °C for the SAF-C501 Symbol Input low voltage (except EA, VIL RESET) Limit Values Unit Test Condition min. max. – 0.5 0.2 VCC – 0.1 V – Input low voltage (EA) VIL 1 – 0.5 0.2 VCC – 0.3 V – Input low voltage (RESET) VIL 2 – 0.5 0.2 VCC + 0.1 V – Input high voltage (except XTAL1, EA, RESET) VIH 0.2 VCC + 0.
Device Specifications C501 10.3 DC Characteristics for C501-1E VCC = 5 V + 10 %, – 15 %; VSS = 0 V; Parameter TA = 0 °C to 70 °C for the SAB-C501 TA = – 40 °C to 85 °C for the SAF-C501 Symbol Limit Values min. max. Unit Test Condition Input low voltage (except EA/VPP, RESET) VIL – 0.5 0.2 VCC – 0.1 V – Input low voltage (EA/VPP) VIL 1 – 0.5 0.1 VCC – 0.1 V – Input low voltage (RESET) VIL 2 – 0.5 0.2 VCC + 0.1 V – Input high voltage (except XTAL1, EA/VPP, RESET) VIH 0.2 VCC + 0.
Device Specifications C501 Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V.
Device Specifications C501 10.4 AC Characteristics for C501-L / C501-1R / C501-1E VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 °C to 70 °C for the SAB-C501 TA = – 40 °C to 85 °C for the SAF-C501 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 12 MHz Clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. max. min. max.
Device Specifications C501 AC Characteristics for C501-L / C501-1R / C501-1E (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values 12 MHz Clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. max. min. max.
Device Specifications C501 10.5 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 °C to 70 °C for the SAB-C501 TA = – 40 °C to 85 °C for the SAF-C501 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 24 MHz Clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. max. min. max.
Device Specifications C501 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values 24 MHz Clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. max. min. max.
Device Specifications C501 10.6 AC Characteristics for C501-L40 / C501-1R40 VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 °C to 70 °C for the SAB-C501 TA = – 40 °C to 85 °C for the SAF-C501 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 40 MHz Clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz min. max. min. max.
Device Specifications C501 AC Characteristics for C501-L40 / C501-1R40 (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values 40 MHz Clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz min. max. min. max.
Device Specifications C501 t LHLL ALE t AVLL t PLPH t LLPL t LLIV t PLIV PSEN t AZPL t PXAV t LLAX t PXIZ t PXIX Port 0 A0 - A7 Instr.
Device Specifications C501 t WHLH ALE PSEN t LLDV t LLWL t RLRH RD t RLDV t AVLL t RHDZ t LLAX2 t RLAZ Port 0 A0 - A7 from Ri or DPL t RHDX Data IN A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.
Device Specifications C501 t WHLH ALE PSEN t LLWL t WLWH WR t QVWX t AVLL t WHQX t LLAX2 A0 - A7 from Ri or DPL Port 0 t QVWH A0 - A7 from PCL Data OUT Instr.IN t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 Data Memory Write Cycle t CLCL VCC- 0.5V 0.45V 0.7 VCC 0.2 VCC- 0.
Device Specifications C501 10.7 ROM Verification Characteristics for C501-1R ROM Verification Mode 1 Parameter Symbol Limit Values min. max. Unit Address to valid data tAVQV – 48tCLCL ns ENABLE to valid data tELQV – 48tCLCL ns Data float after ENABLE tEHQZ 0 48tCLCL ns Oscillator frequency 1/tCLCL 4 6 MHz P1.0 - P1.7 P2.0 - P2.4 Address t AVQV Port 0 Data OUT t ELQV t EHQZ P2.7 ENABLE MCT00049 Address: P1.0 - P1.7 = A0 - A7 P2.0 - P2.4 = A8 - A12 Data: P0.0 - P0.
Device Specifications C501 10.8 OTP Programming and Verification Characteristics for C501-1E VCC = 5 V ± 10%, VSS = 0 V, TA = 21 °C to + 27 °C Parameter Symbol Limit Values min. max. Unit Programming supply voltage VPP 12.5 13.
Device Specifications C501 P1.0 - P1.7 P2.0 - P2.4 Programming Verification Address Address t AVQV Port 0 Data Data t DVGL t GHDX t GHAX t AVGL ALE/PROG t GLGH t GHGL t SHGL t GHSL Logic 1 EA/ V PP Logic 0 t EHSH t ELQV P2.
Device Specifications C501 AC Inputs during testing are driven at VCC – 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing measurements are made at VIHmin for a logic ‘1’ and VILmax for a logic ‘0’. AC Testing: Input, Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH / VOL level occurs. IOL / IOH ≥ ± 20 mA.
Device Specifications C501 Crystal Oscillator Mode Driving from External Source C 3.5 - 40 MHz XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 C XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15 N.C. External Oscillator Signal XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15 C = 20 pF 10 pF (incl.
Device Specifications C501 10.9 Package Outlines GPD05883 Plastic Package, P-DIP-40 for C501G-L / C501G-1R (Plastic Dual in-Line Package) P-DIP-40 Package Outlines Sorts of Packing Package outlines for tubes, trays etc.
Device Specifications C501 GPL05882 Plastic Package, P-LCC-44 – SMD for C501G-L / C501G-1R / C501G-1E (Plastic Leaded Chip-Carrier) P-LCC-44 Package Outlines Sorts of Packing Package outlines for tubes, trays etc.
Device Specifications C501 GPM05957 Plastic Package, P-MQFP-44 – SMD for C501G-L / C501G-1R (Plastic Metric Quad Flat Package) P-MQFP-44 Package Outlines Sorts of Packing Package outlines for tubes, trays etc.
Index C501 11 External bus interface . . . . . . . . . . . . . . ALE signal . . . . . . . . . . . . . . . . . . . . . Overlapping of data/program memory Program memory access . . . . . . . . . . Program/data memory timing. . . . . . . PSEN signal . . . . . . . . . . . . . . . . . . . . Role of P0 and P2 . . . . . . . . . . . . . . . Index Note : Bold page numbers refer to the main definition part of SFRs or SFR bits. A Absolute maximum ratings . . . . . . . . . . 10-1 AC . . . . . . . . . . . . . . . .
Index C501 M M0 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-17 M1 . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-17 Memory organization . . . . . . . . . . . . . . . 3-1 Data memory . . . . . . . . . . . . . . . . . . . 3-2 General purpose registers . . . . . . . . . 3-2 Memory map. . . . . . . . . . . . . . . . . . . . 3-1 Program memory . . . . . . . . . . . . . . . . 3-2 PSEN signal. . . . . . . . . . . . . . . . . . . . . . 4-4 PSW. . . . . . . . . . . . . . . . . . . . .
Index C501 TCON . . . . . . . . . . . . . . . 3-4, 3-5, 6-16, 7-4 TF0 . . . . . . . . . . . . . . . . . . . . . 3-5, 6-16, 7-4 TF1 . . . . . . . . . . . . . . . . . . . . . 3-5, 6-16, 7-4 TF2 . . . . . . . . . . . . . . . . . . . . . 3-5, 6-24, 7-5 TH0. . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-15 TH1. . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-15 TH2. . . . . . . . . . . . . . . . . . . . . 3-4, 3-5, 6-23 TI . . . . . . . . . . . . . . . . . . . . . . 3-5, 6-31, 7-5 Timer/counter . . .
