. ERTEC 200 Enhanced Real-Time Ethernet Controller Manual Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change Page 1 ERTEC 200 Manual Version 1.1.
Edition (04/2007) Disclaimer of Liability We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly. Necessary corrections are included in subsequent editions. Suggestions for improvement are welcomed. Copyright © Siemens AG 2006.
Preface Target Audience of this Manual This manual is intended for hardware developers who want to use the ERTEC 200 for new products. Experience working with processors and designing embedded systems and knowledge of Ethernet are required for this. It described all ERTEC function groups in details and provides information that you must take into account when configuring your own PROFINET IO device hardware. The manual serves as a reference for software developers.
This manual will be updated as required. You can find the current version of the manual on the Internet at http://www.siemens.com/comdec. Guide To help you quickly find the information you need, this manual contains the following aids: o A complete table of contents as well as a list of all figures and tables in the manual are provided at the beginning of the manual. o A glossary containing definitions of important terms used in the manual is located following the appendices.
Contents 1 Introduction ............................................................................................................................9 1.1 Applications of the ERTEC 200 .............................................................................................................. 9 1.2 Features of the ERTEC 200 ................................................................................................................... 9 1.3 Structure of the ERTEC 200....................................
4.4.2 F-Timer Register Description ......................................................................................................... 44 4.5 Watchdog Timers ................................................................................................................................... 45 4.5.1 Watchdog Timer 0.......................................................................................................................... 45 4.5.2 Watchdog Timer 1...........................................
11.1.3 ETM9 Registers ............................................................................................................................. 94 11.2 Trace Interface ....................................................................................................................................... 95 11.3 JTAG Interface ....................................................................................................................................... 95 11.4 Debugging via UART...................
List of Figures Figure 1: ERTEC 200 Block Diagram .................................................................................................................... 10 Figure 2: ERTEC 200 Package Description .......................................................................................................... 11 Figure 3: Structure of ARM946E-S Processor System ..........................................................................................
1 Introduction The ERTEC 200 is intended for the implementation of PROFINET devices with RT and IRT functionality. With its integrated ARM946 processor and 2-port Ethernet switch with integrated PHYs and the option to connect an external host processor system to a local bus interface, it meets all the requirements for implementing PROFINET devices with integrated switch functionality. 1.1 1.
1.3 Structure of the ERTEC 200 The figure below shows the function groups with the common communication paths.
1.4 ERTEC 200 Package The ERTEC 200 is supplied in an FBGA package with 304 pins. The distance between the pins is 0.8 mm. The package dimensions are 19 mm x 19 mm. Figure 2: ERTEC 200 Package Description Soldering instructions for the ERTEC 200 can be found in the following documents: /10/ Soldering instructions for lead-based block. /11/ Soldering instructions for lead-free block. /12/ Code description for soldering.
1.5 Signal Function Description ERTEC 200 Pin Description The ERTEC 200 Ethernet communication block is available in a 304-pin FBGA package. The signal names of the ERTEC 200 are described in this section. 1.5.1 GPIO 0 to 31 and Alternative Functions Various signals are multiplexed on the same pin. These multiplexed signals can contain up to four different functions. The alternative functions are assigned in GPIO registers GPIO_PORT_MODE_L and GPIO_PORT_MODE_H (see Section 4.2.2).
No. Signal Name Alternative Function 1 Alternative Function 2 Alternative Function 3 I/O (Reset) Pull- PIN No.
1.5.4 No. Clock and Reset Signal Name I/O (Reset) Pull- PIN No. Comment CLOCK / RESET GENERATION 42 43 44 45 CLKP_A CLKP_B F_CLK REF_CLK 46 RESET_N 1.5.5 No. I (I) O I (I) Dependent on PIN CONFIG[1] I (I) B14 D14 B13 A15 Quartz connection Quartz connection F_CLK for F-counter Tristate or reference clock output, 25 MHz up B7 PowerOn reset Pull- PIN No. Test Pins Signal Name I/O (Reset) Comment TEST 47 48 49 50 1.5.6 No.
No. Signal Name Alternative Reset Function I/O (Reset) Pull- PIN No.
No. Signal Name Alternative Reset Function I/O (Reset) Pull- PIN No. Comment EMIF (External Memory Interface) 109 110 111 WR_N RD_N CS_PER0_N O (O) O (O) 112 113 114 115 116 117 118 119 120 121 122 123 124 CS_PER1_N CS_PER2_N CS_PER3_N BE0_DQM0_N BE1_DQM1_N BE2_DQM2_N BE3_DQM3_N RDY_PER_N CLK_SDRAM CS_SDRAM_N RAS_SDRAM_N CAS_SDRAM_N WE_SDRAM_N O (O) O (O) O (O) O (O) O (O) O (O) O (O) I (I) B (O) O (O) O (O) O (O) O (O) 1.5.7 No.
No. Function 1 Function 2 Function 3 Function 4 LBU PHY Debug and GPIO[44:32] Config (6,5,2)=011b ETM Trace and GPIO[44:32] Config (6,5,2)=101b Reserved Config (6,5,2)=xx0b IO (Reset See Config [6,5,2]) Pull - PIN No.
No. Function 1 Function 2 Function 3 Function 4 LBU PHY Debug and GPIO[44:32] Config (6,5,2)=011b ETM Trace and GPIO[44:32] Config (6,5,2)=101b Reserved Config (6,5,2)=xx0b IO (Reset See Config [6,5,2]) Pull - PIN No.
No. Signal Name I/O Pull- PIN No. Comment PHY1 and PHY2 196 197 198 P1SDxN P1SDxP P1TDxN I I O F19 G19 C22 199 P1TDxP O C21 P1RDxN P1RDxP P1VSSATX2 P1TxP P1TxN P1VSSATX1 P1RxP P1RxN P1VSSARX P1VDDARXTX GND33ESD VDD33ESD DGND2 DVDD2 DVDD1 DGND1 I I I B B I B B I I I I I I I I E21 E22 K18 J22 J21 K17 G21 G22 J17 J19 H18 F22 G17 H19 G18 H21 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 1.5.
Signal description: IO = I: B: Signal direction from perspective of the application Input Bidirectional O: P: Output Power supply Pull- = Internal pull-up/pull-down resistor connected to the signal pin up: Internal pull-up dn: Internal pull-down PU/PD = External resistances necessary, depending on application PU: External pull-up PD: External pull-down _N in last position of signal name signifies: Signal is Low active Example: INTA_N Note: (1) The BOOT[3:0] pins are read into the “BOOT_REG” sys
2 ARM946E-S Processor The ARM946E-S processor is implemented in the ERTEC 200. This description is based on /1/ and /2/. 2.1 Structure of ARM946E-S An ARM946E-S processor system is used. The figure below shows the structure of the processor. In addition to the processor core, the system contains one data cache, one instruction cache, a memory protection unit (MPU), a system control coprocessor, and a tightly coupled memory. The processor system has an interface to the integrated AHB bus.
2.2 Description of ARM946E-S The ARM946E-S processor system is a member of the ARM9 Thumb family. It has a processor core with Harvard architecture. Compared to the standard ARM9 family, the ARM946E-S has an enhanced V5TE architecture permitting faster switching between ARM and Thumb code segments and an enhanced multiplier structure. In addition, the processor has an integrated JTAG interface. 2.3 Operating Frequency of ARM946E-S The processor can be operated at 50 MHz, 100 MHz, or 150 MHz.
2.6 Memory Protection Unit (MPU) The memory protection unit enables the user to partition specific memory areas (I-cache, D-cache, or DTCM) into various regions and to assign different attributes to them. A maximum of 8 regions of variable size can be set. If regions overlap, the attributes of the higher region number apply.
2.9.1 Prioritization of Interrupts It is possible to set the priorities of the IRQ and FIQ interrupts. Priorities 0 to 15 can be assigned to IRQ interrupts while priorities 0 to 7 can be assigned to FIQ interrupts. The highest priority is 0 for both interrupt levels. After a reset, all IRQ interrupt inputs are set to priority 15 and all FIQ interrupt inputs are set to priority 7. A priority register is associated with each interrupt input.
The CPU accepts an IRQ-/FIQ request by reading the IRVEC/FIVEQ register. This register contains the binary-coded vector number of the highest priority interrupt request at the moment. Each of the two interrupt vector registers can be referenced using two different addresses. The interrupt controller interprets the reading of the vector register with the first address as an “interrupt acknowledge”. This causes the sequences for this interrupt to be implemented in the ICU logic.
2.9.9 IRQ Interrupts as FIQ Interrupt Sources Interrupts from the IRQ interrupt can be placed on FIQ6 and FIQ7 können. The interrupts of the FIQ interrupt controller are used for debugging, monitoring address area access, and for the watchdog. FIQ interrupts no. 4 and 5 are the interrupts for embedded ICE RT communication. The UART can also be used as a debugger in place of the ICE.
PRIOREG 1 0x0074 ... ... ... ... 4 bytes R/W 0x0000000F .... .... .... PRIOREG15 0x00AC Table 4: Overview of Interrupt Control Register 4 bytes R/W 0x0000000F Priority register 15 2.9.11 ICU Register Description IRVEC Description R Name IRVEC 31:4 Vector ID FIVEC 31:3 Vector ID LOCKREG Bit No. 3–0 7 Bit No. 3–0 7 IRQACK Description Bit No. 3–0 31 - 4 Description For pending, valid interrupt: Binary code of FIQ number. Default vector: Bit[2:0] = 1 For pending valid Bit[31:3] = 0.
FIQACK Description Bit No. 2–0 31 – 3 R IRCLVEC Description Bit No. 3–0 7 Bit No. 0 W Name IRCLVEC unused Bit No. Bit No. Name MASKALL Bit No. 2–0 7–3 Bit No. 7–0 Default: '1' Description '0' = Enable all non-masked IRQ interrupt inputs (consideration given to set mask bits) '1' = Global disable for all IRQ interrupt inputs (independent of the interrupt mask) W Addr.: 0x5000_0024 Default: ---- W Addr.
FIQIRR R Description Bit No. 7–0 Name FIQIRR FIQ_MASKREG Description Bit No. 7–0 Bit No. 15 – 0 Bit No. 15 – 0 Name FIQ_MASKREG Bit No. 15 – 0 Bit No. 15 – 0 EDGEREG Description Bit No. 15 – 0 Default: 0x0000_00FF Addr.: 0x5000_0058 Default:0x0000_01xx Interrupt request register Storage of interrupt requests that have occurred Name IRREG Description Interrupt input 0 to 15 0=Interrupt request inactive/1=Interrupt request active Bit 5, 4, 3, 2 depending on GPIO 31, 30, 1, 0 R/W Addr.
SWIRREG R/W Description Bit No. 15 – 0 Name SWIRREG PRIOREG 0 … PRIOREG 15 Description Bit No. 3–0 Addr.: 0x5000_006C Default: 0x0000_0000 Software interrupt register Specification of interrupt requests Description Interrupt input 0 to 15 0=No interrupt request 1=Set interrupt request R/W …. R/W Addr.: 0x5000_0070 Default: 0x0000_000F Addr.
2.10 ARM946E-S Register The ARM946E-S uses CP15 registers for system control.
3 Bus System of the ERTEC 200 Internally, the ERTEC 200 has two buses. High-performance communication bus (multilayer AHB bus) I/O bus (APB bus) The following function blocks are connected directly to the multilayer AHB bus: ARM946E-S (Master) IRT switch (Master/Slave) LBU (Master) Interrupt controller (Slave) EMIF interface (Slave) DMA-Controller (Master/Slave) The master can access the remaining I/O connected to the low-performance APB bus via an AHB/APB bridge. 3.
4 I/O on APB bus The ERTEC 200 block has multiple I/O function blocks. They are connected to the 32-bit APB I/O bus. The ARM946E-S, DMA controller and LBU interface can access the I/O. The following I/O are available. 8 Kbyte Boot ROM 32-bit GPIO (*) UART SPI interface Timer 0 - 2 F-timer Watchdog System control register (*) The complete 32 bits for GPIO input/output are only available if alternative functions are not assigned.
The following download modes are supported: BOOT(3) 0 0 0 1 1 1 0 0 0 0 0 1 BOOT(2) 0 0 0 0 0 0 0 1 1 1 1 0 BOOT(1) 0 0 1 0 0 1 1 0 0 1 1 1 BOOT(0) 0 1 0 0 1 0 1 0 1 0 1 1 BOOTING OF External ROM with 8-bit data width External ROM with 16-bit data width External ROM with 32-bit data width Fast External ROM with 8-bit data width Fast External ROM with 16-bit data width Fast External ROM with 32-bit data width Reserved Reserved SPI1 UART LBU Reserved Table 8: Selection of Download Source Bootin
4.2 General Purpose I/O (GPIO) Up to 45 General Purpose Inputs/Outputs are available in the ERTEC 200. These are divided into two groups: • GPIO[31:0] 32 bits on the APB I/O bus • GPIO[44:32] 13 bits as an alternative function on the LBU interface The GPIOs [31 : 0] can be used as follows • Inputs • Outputs • One of up to 3 additional special functions (Watchdog, Timer, F-Timer, UART, SPI, ETM and MC-PLL) The direction of the IO can be programmed bit-by-bit in the "GPIO_IOCTRL“ register.
4.2.1 Address Assignment of GPIO Registers The GPIO registers are 32 bits in width. The registers can be read or written to with 8-bit, 16-bit, or 32-bit accesses.
17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 GPIO8_PORT_MODE GPIO9_PORT_MODE GPIO10_PORT_MODE GPIO11_PORT_MODE GPIO12_PORT_MODE GPIO13_PORT_MODE GPIO14_PORT_MODE GPIO15_PORT_MODE GPIO_PORT_MODE_H Description Bit No. 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 Description Name Reserved POLSEL GPIO31 2 POLSEL GPIO30 1 POLSEL GPIO1 0 POLSEL GPIO0 GPIO2_ IOCTRL Description Default: 0x0000_0000 W/R Addr.
GPIO2_ IN Description R Addr.: 0x4000_2528 Bit No. Name Description 31..13 12..0 Reserved GPIO2_IN[44:32] Reserved 0: GPIO inputx = 0, 1: GPIO inputx = 1 4.3 Default: Port assignment Input register for General Purpose IO [44:32] Timer 0/1/2 Three independent timers are integrated in the ERTEC 200. They can be used for internal monitoring of diverse software routines. Each timer is assigned an interrupt that is connected to the IRQ interrupt controller of the ARM946.
4.3.1.1 Timer 0/1 Interrupts The timer 0/1 interrupt is active (High) starting from the point at which the timer value is counted down to 0. The timer interrupt is deactivated (Low) when the reload value is automatically reloaded or the "LOAD“ bit is set by the user. The interrupt is not reset when the reload value 0 is loaded. If the timer is deactivated (Run/XStop = 0), the interrupt is also deactivated.
4.3.3 Address Assignment of Timer Registers The timer registers are 32 bits in width. For read/write access of the timer registers to be meaningful, a 32-bit access is required. However, a byte-by-byte write operation is not intercepted by the hardware.
CTRL_STAT1 Description Bit No. 0 R/W Addr.: 0x4000_2004 Default: 0x0000_0000 Control/status register 1. Configuration and control bits for Timer No. 1. Name Run/xStop *) 1 Load 2 Reload mode *) 3 4 5 Reserved Reserved Status 6 Cascading 31-7 Reserved Description Stop/start of timer: 0: Timer is stopped 1: Timer is running Note: If this bit = 0, the timer interrupt is inactive (0) and the status bit (Bit 5) is reset (0).
RELD_PREDIV Description Bit No. 7:0 15:8 31-16 Name Prediv [7:0] Prediv [15:8] Reserved TIM0 TIM1 Bit No. 31:19 18 Name Timer [31:0] Name Reserved Timer_Mode 16 Run/xStop Addr.: 0x4000_2020 Default: 0x0000_0000 Description Reserved 0: Cyclic 1: Retrigger via UART_RXD signal (for RXD at log.
4.4 F-Timer Function An F-timer is integrated in the ERTEC 200 in addition to the system timers. This timer works independently of the system clock and can be used for fail-safe applications, for example. The F-timer is triggered via the alternative “F_CLK” function at the external “BYP_CLK” input. External triggering is not possible if the ARM946E-S is operated in a reserved test mode (Config[4:3] = 11). The following signal pins are available for the F-timer on the ERTEC 200.
4.4.1 Address Assignment of F-Timer Registers The F-timer registers are 32 bits in width. The registers can be written to in 32-bit width only. F-Counter (Base Address 0x4000_2700) Register Name Offset Address Address Area Access Default Description F-COUNTER-VAL 0x0000 4 bytes R 0x00000000 F-counter value register F-COUNTER-RES 0x0004 4 bytes W 0x00000000 Reset register for F-counter Table 11: Overview of F-Timer Registers 4.4.
4.5 Watchdog Timers Two watchdog timers are integrated in the ERTEC 200. The watchdog timers are intended for stand-alone monitoring of processes. The working clock of 50 MHz is derived from the PLL the same as the processor clock. 4.5.1 Watchdog Timer 0 Watchdog timer 0 is a 32-bit down-counter to which the WDOUT0_N output is assigned. This output can be used at the GPIO[15]-pin as an alternative function (see GPIO and signal descriptions). The timer is locked after a reset.
4.5.6 Watchdog Registers The watchdog registers are 32 bits in width. For read/write access of the watchdog registers to be meaningful, a 32-bit access is required. However, a byte-by-byte write operation is not intercepted by the hardware. To prevent the watchdog registers from being written to inadvertently, e.g., in the event of an undefined computer crash, the writable watchdog registers are provided with write protection. The upper 16 bits of the registers are so-called key bits.
RELD0_LOW Description Bit No. 15-0 31-16 R/W Name Reload0 [15:0] Key bits RELD0_HIGH Description Bit No. 15-0 31-16 R/W Bit No. 31-0 Name Reload1 [19:4] Key bits Bit No. 31-0 Addr.: 0x4000_210C Default: 0x0000_FFFF Description Reload value for bits 19:4 of watchdog counter 1. Key bits for writing to this register (read=0). If bits 31-16=9876h, writing of bits 0-15 of this register has an effect; otherwise, no effect. R/W Addr.: 0x4000_2110 Default: 0x0000_FFFF Reload register 1_High.
4.6 UART Interface A UART interface is implemented in the ERTEC 200. The inputs and outputs of the UART interface are available as an alternative function at GPIO port [12:8]. For this purpose, the I/O must be assigned to the relevant inputs and outputs and the alternative function must be assigned (see GPIO register description). If the UART is used, the pins are no longer available as standard I/O. The data bit width for read/write access on the APB bus is 8 bits.
The baud rate generation is derived from the internal 50 MHz APB clock. The resulting deviations from the standard baud rates used are so small that a secure data transmission is achieved.
4.6.2 UART Register Description UARTDR Description Bit No. 7–0 R/W Addr.: 0x4000_2300 Default: 0x-- UART data registers Name ------- Description WRITE: If FIFO is enabled, the written data are entered in the FIFO. If FIFO is disabled, the written data are entered in the Transmit holding register (the first word in the Transmit FIFO). READ: If FIFO is enabled, the received data are entered in the FIFO.
UARTLCR_H Description Bit No. 0 R/W Addr.: 0x4000_2308 Default: 0x00 UART line control register high byte bit rate and control register bits 22 to 16 Name BRK Send break = 1 A LOW level is sent continuously at the Transmit output. 1 PEN Parity enable = 1 Parity check and generation are enabled. 2 EPS 3 STP2 4 FEN If PEN = 1 Even parity select = 1 Even parity (1) for check and generation. Even parity select = 0 Odd parity (0) for check and generation.
UARTCR Description Bit No. 0 R/W Addr.: 0x4000_2314 Default: 0x00 UART control registers Name UARTEN Description UART Enable = 1 UART sending/receiving of data is enabled 1 SIREN 2 SIRLP SIR enable = 1 IrDA SIR Endec is enabled.
UARTIIR/UARTICR Description Bit No. 0 R/W Addr.: 0x4000_231C Default: 0x00 UART interrupt identification register (read) UART interrupt clear register (write) Name MIS (Read) Modem Interrupt Status This bit is set if UARTMSINTR is active. 1 RIS (Read) Receive Interrupt Status This bit is set if UARTRXINTR is active. 2 TIS (Read) Transmit Interrupt Status This bit is set if UARTTXINTR is active. 3 RTIS (Read) Receive Timeout Interrupt Status This bit is set if UARTRTINTR is active.
4.7 Synchronous Interface SPI An SPI interface is implemented in the ERTEC 200. The inputs and outputs of the SPI interface are available as an alternative function at GPIO port [23:16]. For this purpose, the I/O must be assigned to the relevant inputs and outputs and the alternative function must be assigned (see GPIO register description). If the SPI interface is used, the pins are no longer available as standard GPIO. The base frequency for the internal bit rate generation is the 50 MHz APB clock.
For the synchronous clock output of the SPI interface, the following frequencies are calculated according to the assigned SPI registers: 50 MHz SCLKOUT = ----------------------------CPSDRV * (1+SCR) The SPI parameters can assume the following values: CPSDRV SCR From 2 to 254 From 0 to 255 This yields a frequency range of • • 769 Hz 25 MHz[Master]/8.
4.7.2 SPI Register Description SSPCR0 R/W Description Bit No. 3-0 5-4 6 7 15-8 Addr.: 0x4000_2200 Default: 0x0000 Control register 0. Configuration frame format and baud rate for SPI.
15-7 Reserved Read: Value is undefined Write: Should always be written with zero ------- SSPDR R/W Addr.: 0x4000_2208 Default: 0x---- Description SPI data register Bit No. Name Description Transmit/Receive FIFO 15-0 DATA (15:0) Read = Receive FIFO Write = Transmit FIFO (If < 16 bits of data, the user must write the data to the Transmit FIFO in the proper format. When data are read, they are read out correctly from the Receive FIFO.) SSPSR R Addr.
SSPIIR/SSPICR Description Bit No. 0 1 2 15-3 15-0 4.8 R/W Addr.
UART_CLK 0x0070 4 bytes R/W 0x00000000 UART clock selection 50MHz/6MHz Table 16: Overview of System Control Registers 4.8.2 System Control Register Description ID_REG R Description Bit No. 31..16 15..8 7..0 Name ERTEC200-ID HW-RELEASE METALL-FIX Description Bit No. 31..7 6 .. 1 0 Description ERTEC 200 identifier: 4027h HW release: 01h Metal fix: 00h R Addr.: 0x4000_2604 Name Reserved BOOT[3:0] Description Reserved Reading of Boot[3] pin R Addr.
PLL_STAT_REG Description Bit No. 31..18 17 R/W Name Reserved INT_MASK_LOSS 16 INT_MASK_LOCK 15..6 5 Reserved INT_QVZ_EMIF_ STATE 4 3 Reserved INT_LOSS_STATE 2 INT_LOCK_STATE 1 PLL_INPUT_CLK_LO SS 0 PLL_LOCK QVZ_AHB_ADR Description Bit No. 31:0 Bit No.
QVZ_AHB_M Description Bit No. 31:4 3 2 1 0 R Name Reserved QVZ_AHB_DMA QVZ_AHB_IRT QVZ_AHB_LBU QVZ_AHB_ARM946 QVZ_APB_ADR Description Bit No. 31:0 Name QVZ_EMIF_ADR Addr.: 0x4000_2634 Default: 0x0000_0000 Description Address R Addr.: 0x4000_2638 Default: 0x0000_0000 Description Address R/W Addr.
ARM9_CTRL Description Bit No. 31:14 13 12 R/W 11 DBGEN 10 MICEBYPASS 9 INITRAM 8:0 SYSOPT[8:0] ARM9_WE Description Bit No. 31:1 0 Name ---- Description Name Reserved REVISION_ID VERSION_ID DEBUG_ID Description 1 Default: 0x0000_0000 Description Reserved Write enable for ARM9_CTL register 1: ARM9_CTRL can be write accessed. 0: ARM9_CTRL is read-only. R/W Addr.: 0x4000_2658 Default: 0x0001_01xx Tag number of current ASIC switching state. PHY_CONFIG 15 :14 13 Addr.
12:10 P2_PHY_MODE 9 P2_FX_ MODE 8 P2_PHY_ENB 7:6 5 P1_AUTOMDIXEN 4:2 P1_PHY_ MODE 1 P1_FX_ MODE 0 P1_PHY_ENB PHY_ STATUS Description Bit No. 31:9 8 7:1 0 Name P2_PWRUPRST UART_CLK Bit No. 31:1 0 R Addr.
5 General Hardware Functions 5.1 Clock Generation and Clock Supply The clock system of the ERTEC 200 basically consists of four clock systems that are decoupled through asynchronous transfers. This includes the following clock systems: • ARM946E-S together with AHB bus, APB bus, and IRT • LBU • JTAG Interface • PHYs and Ethernet MACs 5.1.1 Clock Supply in ERTEC 200 The required clocks are generated in the ERTEC 200 by means of internal PLL and/or through direct infeed.
5.1.2 JTAG Clock Supply The clock supply for the JTAG interface is implemented using the JTAG_CLK pin. The frequency range is between 0 and 10 MHz. The boundary scan and the ICE macro cell of the ARM946E-S are enabled via the JTAG interface. 5.1.3 Clock Supply for PHYs and Ethernet MACs Both Ethernet MACs are connected to the integrated PHYs via the MII interface. The clock supply of the PHYs takes place via the internal 25MHz clock CLKP_A.
f/MHz tLOCK = 645 µs 300 active Reset Power-up PLL t/µs 35 Figure 11: Power-Up Phase of the PLL The lock status of the PLL is monitored by the hardware. Loss of the input clock and PLL not locked status is signaled with interrupt FIQ3. The state of the PLL can also be read out in the PII_STAT_REG system control register. A filter is integrated at the RESET_N input, which suppresses spikes up to 5 ns. The SRST_N reset signal is available for the debugger.
5.3 Address Space and Timeout Monitoring Monitoring mechanisms are incorporated in the ERTEC 200 for detection of incorrect addressing, illegal accesses, and timeout. The following I/O are monitored: • AHB bus • APB bus • EMIF 5.3.1 AHB Bus Monitoring Separate address space monitoring is assigned for each of the four AHB masters (ARM946, IRT, DMA, LBU).
Config [6] - Config [5] - Config [4] - Config [3] - Config [2] - Config [1] 1 0 - 1 - - 0 - - 0 - - 0 - 1 - - - 0 - 0 - - - 0 - 0 1 - - 1 - 1 0 - - 1 - 1 - 1 - 0 0 1 1 0 1 0 1 1 - - Meaning REF_CLK tristate REF_CLK output (25 MHz) LBU = On, LBU-CFG: LBU_WR_N has read/write control LBU = On, LBU-CFG: Separate read and write line LBU = On, LBU_POL_RDY: LBU_RDY_N is high active LBU = On, LBU_POL_RDY: LBU_RDY_N is low active LBU = off, GPIO44-32 = on int.
6 External Memory Interface (EMIF) In order to access an external memory area, an External Memory InterFace is incorporated in the ERTEC 200. The interface contains one SDRAM memory controller and one SRAM memory control each for asynchronous memory and I/O. Both interfaces can be assigned separately as active interfaces. That is, the data bus is driven actively to High at the end of each access. The internal pull-ups keep the data bus actively at High. External pull-ups are not required.
6.1 Address Assignment of EMIF Registers The EMIF registers are 32 bits in width. These registers can only be written to with double words.
SDRAM Bank Config Description W/R Addr.: 0x7000_0008 Default: 0x0000_20A0 SDRAM bank config register Bit No. 31..14 13* Name Reserved CL 12..11 10..8* Reserved ROWS 7 6..4 Reserved IBANK 3 2..
Async Bank 0 Config Async Bank 1 Config Async Bank 2 Config Async Bank 3 Config Description W/R W/R W/R W/R Addr.: 0x7000_0010 Addr.: 0x7000_0014 Addr.: 0x7000_0018 Addr.: 0x7000_001C Default: 0x3FFF_FFF2 Default: 0x3FFF_FFF2 Default: 0x3FFF_FFF2 Default: 0x3FFF_FFF2 Setting of timing and data bus width for access via asynchronous interface CS_PER0_N CS_PER3_N. (The AHB clock is 20 ns in length) Bit No. 31 Name EWS_XAS 30 EW 29..26 W_SU 25..20 W_STROBE 19..17 W_HOLD 16..13 R_SU 12..
Extended Config Description W/R Addr.: 0x7000_0020 Default: 0x0303_0000 Setting of additional functionalities Bit No. 31 30 Name Reserved TEST_1 29 TEST_2 28..26 25 Reserved ADB 24 ASDB 23..20 19 Reserved TEST_3 18 17..16 Reserved BURST_LENGTH 15 14 Reserved TRCD/TCD 13..9 8 Reserved SDSIZE 7 ATIRQ 6..
7 Local Bus Unit (LBU). The ERTEC 200 can also be operated from an external host processor. The LBU bus interfaces are available for this purpose: The bus system is selected using the CONFIG[2] input pin. CONFIG[2] = 0 CONFIG[2] = 1 activated) LBU bus system is active LBU bus system is inactive (supplemental function PHY debug, ETM trace, GPIO[44:32] can be The LBU is a 16-bit data interface. The following signal pins are available for the LBU on the ERTEC 200.
The four segments are addressed via the two LBU_SEG[1:0] inputs. LBU_SEG[1 : 0] Addressed Segment 00 LBU_PAGE0 01 LBU_PAGE1 10 LBU_PAGE2 11 LBU_PAGE3 Copyright © Siemens AG 2007. All rights reserved. Technical data subject to change 75 ERTEC 200 Manual Version 1.1.
7.1 Page Range Setting The page size of each page is set in the PAGEx_RANGE_HIGH and PAGEx_RANGE_LOW range registers (x = 0 to 3). Together, the two page range registers yield a 32-bit address register. The size of the page varies between 256 bytes and 2 MBytes. Therefore, Bits 0 to 7 and Bits 22 to 31 of the PAGEx_RANGE register remain unchanged at a value of 0 even if a value of 1 is entered.
7.
7.4 Page Control Setting The user can use the page control register to set the type of access to the relevant page. Certain areas of the ERTEC 200 must be implemented with a 32-bit data access in order to ensure data consistency. For other areas, an 8-bit or 16bit data access is permitted. The following table shows which ERTEC 200 address areas require 32-bit access.
7.5.
7.5.
7.5.
7.5.
7.7 Address Assignment of LBU Registers The LBU registers are 16 bits in width. These registers can only be written to with words. The LBU paging configuration registers are addressed via the "LBU_CS_R_N” input.
LBU_P0_RG_H LBU_P1_RG_H LBU_P2_RG_H LBU_P3_RG_H Description Bit No. 15..0 W/R W/R W/R W/R Name Description Description Upper 16 bits for area setting 15:6 are read-only (value: 000h) 5:0 are read/write accessible W/R W/R W/R W/R Name Description Default: 0x0000_0000 Default: 0x0000_0000 Default: 0x0000_0000 Default: 0x0000_2000 Description Lower 16 bits for offset setting 15:8 are read/write accessible 7:0 are read-only (value: 00h) W/R W/R W/R W/R Addr.: LBU_CS_R_N+0x06 Addr.
8 DMA-Controller The ERTEC 200 has a 1-channel DMA controller. This enables data to be transferred without placing an additional load on the ARM946E-S.
8.1 DMA Register Address Assignment The DMA registers are 32 bits in width. The registers can be written to with 32-bit accesses only. Only the ARM946E-S processor can access the registers.
(DMAC0ConfReg) Channel Config (*) Description W/R Addr.: 0x8000_000C Default: 0x0000_0000 Control Bits. 31 START/ABORT 30 29 28..27 Reserved INTR_ENABLE (****) SYNCHRONIZATION 26..24 23..22 S_ADDR_MODE 21..19 S_DMA_REQU 18..16 S_WIDTH 15..14 D_ADDR_MODE 13..11 D_DMA_REQU 10..8 D_WIDTH 7..4 D_DELAY(***) 3..
9 Multiport Ethernet PHY A 2-fold multiport PHY (Physical Layer Transceiver) that supports the following transfer modes is integrated in the ERTEC 200: • 10BASE-T • 100BASE-TX • 100BASE-FX These transfer modes are available separately for each port and can be set differently. The PHY is compatible with the following standards: • IEEE802.3 • IEEE802.3u • ANSI X3.263-1995 • ISO/IEC9314 The data interface with the Ethernet MACs takes place via MII.
• • • • • • • • • • P1/2_PHYADDRESS4..0 P1/2_PHYMODE2..0 P1/2_MIIMODE1..0 P1/2_SMIISOURCESYNC P1/2_FXMODE P1/2_AUTOMIDIXEN P1/2_NPMSGCODE2..0 P1/2_PHYENABLE REG2OUIIN15..0 REG3OUIIN15..
Power-State is approximately 15 mW per PHY. The Low-Power-Mode is exited again with Link-Pulses or Packets on the MII interface. The digital modes are reinitialized, but the configuration is not saved again. When the Power Down state is exited, a 256-µs reset is generated internally to stabilize the PLL before the PHY is again ready for operation. Both PHYs generate one interrupt each, which are placed on interrupt input IRQ9 of the ARM946E-S interrupt controller.
10 Memory Description This section presents a detailed description of the memory areas of all integrated function groups. 10.1 Memory Partitioning of the ERTEC 200 The table below lists the AHB masters along with their options for accessing various memory areas. Start- and Endadress Seg.
10.2 Detailed Memory Description The table below presents a detailed description of the memory segments. Mirrored segments should not be used for addressing to ensure compatible memory expansion at a later date. Segment 0 Contents Boot-ROM (0-8kB) or EMIF-SDRAM (0-128MB) or EMIF-Memory(0-64MB) or Locked I-Cache (2/4/6kB) Größe 256 MB Adressbereich 0000_0000 0FFF_FFFF Beschreibung After Reset: Boot-ROM (8kB physical.; memory swap=00b); After memory swap: EMIF-SDRAM (128MB physical.
Segment Contents Größe Adressbereich 5 ARM-ICU 256 MB 5000_00005FFF_FFFF 6 Not used 256 MB 6000_00006FFF_FFFF 7 EMIF-Register 256 MB 7000_00007FFF_FFFF 8 DMA-Register 256 MB 8000_0000FFFF_FFFF Not used 1,75 GB 9000_0000FFFF_FFFF 9 - 15 Beschreibung ARM – Interrupt-Controller 128 Byte physical Note2 Steuer-Register for external Memory-Interface 64 Byte physical Note2 DMA-Controller 16 Byte physikalisch Note2 Table 34: Detailed Description of Memory Segments Note: 1.
11 Test and Debugging 11.1 ETM9 Embedded Trace Macrocell An ETM9 module is integrated in the ARM946E-S of the ERTEC 200 to enable the instruction code and data to be traced. The ARM946E-S supplies the ETM module with the signals needed to carry out the trace functions. The ETM9 module is operated by means of the Trace interface or JTAG interface. The trace information is stored in an internal FIFO and forwarded to the debugger via the interface.
11.2 Trace Interface The trace interface is parameterized, enabled, and disabled by means of a connected debugger (e.g. by Lauterbach) on the JTAG interface. A Trace port is provided in the ERTEC 200 for tracing internal processor states: • PIPESTA [2:0] • TRACESYNC • TRACECLK • TRACEPKT[7:0] The PIPESTA[2:0], TRACEPKT[7:0], and TRACESYNC signals are alternative signal pins at the LBU interface. The trace interface is activated with the configuration pins CONFIG[6,5,2] = 101.
12 Miscellaneous 12.
12.2 References: /1/ /2/ /3/ /4/ /5/ /6/ /7/ /8/ /9/ /10/ /11/ /12/ /13/ /14/ Technical Reference Manual ARM946E-S REV1 16 February 2001 (DDI 0201A_946ES.PDF); Technical Reference Manual ARM946E-S 16 December 1999 (DDI_ 0165A_9E-S_TRM. PDF); AHB PCI Bridge Revision2.5 08 July 2002 (amba2pci_rev2.5.pdf); AMBA Specification (Revision 2.
