Technical data

Example 2:
In this example the CPU detects an addressing error when executing the
"A I x.y" operation in OB 1. This leads to the processing of OB 25. As a
result of an STP operation in PB 5, the CPU goes into the STOP mode (see
Fig. 5-4).
Continued on next page
CYCLE
ADF
JU PB 5
OB 25
0100
0105
0106
PB 5
STP
1000
1007
ADF
AIx.y
OB 1
0010
001A
CDB16
Fig. 5-4 Example 2 of evaluating the ISTACK
Control Bits and Interrupt Stack
CPU 928B Programming Guide
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