Technical data

8.1 Structure of the Memory Area
The memory area of the CPU 928B is basically divided into the
following areas:
Memory area Length Width
User memory: For OBs, FBs, FXs, PBs, SBs, DBs, DXs
max. 32x2
10
words 16 bits
DB-RAM: For data blocks, shift registers
23x2
10
words 16 bits
Flags: S
1024 bytes 8 bits
Interface data area: RI, RJ
System data area: RS, RT
Counters: C
Timers: T
each 256 words
each 256 words
256 words
256 words
16 bits
16 bits
16 bits
16 bits
Flags: F
256 bytes 8 bits
Process input and
output image: PII, PIQ
each 128 bytes 8 bits
Peripheral I/O area,
divided into:
P peripherals
O peripherals
IM 3
IM 4
IPC flags
Coordinator module
Pages (CP, IP, 923C)
Distributed I/Os
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
2048 bytes
768 bytes
8 bits
Refer to the memory map in the next section for the exact
addresses of the areas.
Note
With STEP 5, you should never access a memory cell within an
operand area (e.g. flags) directly using the absolute address of this
memory area, but always relative to the base address of the
operand area.
The base addresses of all operand areas are in the system data
area (RS area - see "system data assignment").
Table 8-1 Structure of the memory area
Structure of the Memory Area
CPU 928B Programming Guide
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