Technical data

8.2 Address Distribution in the CPU 928B
Flags
PII/PIQ area
Peripheral I/Os
(digital/analog
CP/IP)
S5 bus
System transfer data (RI/RJ areas),
system data (RS/RT areas),
counters, timers
S flags
User memory
DB-RAM
EE00
EF00
F000
FFFF
RAM or EPROM
submodule, can be
plugged into the CPU
0
000
7
FFF
8
000
D
D7F
D
D80
E400
E
800
E7FF
DB 0 (block address lists)
E
3FF
System RAM, interna
l
to the CPU
(see also Fig. 8-2)
E
DFF
EEFF
EFFF
(see also Fig. 8-3)
B
it no.15 8 7 0
15
70
max. 32 x 2
10
words
10
words
23 x 2
Fig. 8-1 Address distribution in the CPU 928B - overview
8
Address Distribution in the CPU 928B
CPU 928B Programming Guide
C79000-B8576-C898-01
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