Technical data

EA1E
EA27
EA36
CPU identifier 1 PG interface software release
127
39
54
81
30
31
32
33
34
35
36
37
38
55
56
59
60
63
64
80
79
128
129
130
131
132
133
134
135
136
137
EA21
EA20
EA1F
EA22
EA23
EA24
EA25
EA26
EA89
EA37
EA38
EA3B
EA3C
EA3F
EA40
EA7F
EA80
EA81
EA82
EA83
EA84
EA85
EA86
EA87
EA88
EA50
EA4E
EA51
Length of the block header information
Counter for 1 hour (to 3599 sec, hex)
Reserved for handling block
Reserved for user purposes
Reserved for system program
Base address of the DX address list
Base address of the FX address list
Base address of the DB address list
Base address of the SB address list
Base address of the PB address list
Base address of the FB address list
Base address of the OB address list
"Closed loop control" ID
Condition codeword "disable all interrupts"
Condition codeword "delay all interrupts"
"Process image updating" ID
Condition codeword "disable individual time interrupts"
Condition codeword "delay individual time interrupts"
Additional error ID if bit FE-5 is set in RS 8
Reserved for system program
138
140
139 EA8B
EA8A
EA8CCondition codeword "write and delete blocks"
Alternative loading of data blocks
EA8D
EA8F
EA90
EA91
EAFF
141
143
144
145
255
Fig. 8-7 RS area memory map (part 2)
8
User Memory Organization in the CPU 928B
CPU 928B Programming Guide
C79000-B8576-C898-01
8 - 17