Technical data

9.2.1
LIR/TIR: Loading to or
Transferring from a 16-Bit
Memory Area Indirectly
The following table shows which register numbers you can use with
the CPU 928B for the LIR and TIR operations and how these are
assigned.
Register no. Register assignment (each 16 bits wide)
0
ACCU-1-H (left word of ACCU1, bits 16 to 31)
1)
1
ACCU-1-L (right word of ACCU1, bits 0 to 15)
1)
2
ACCU-2-H
3
ACCU-2-L
5
Block stack pointer (offset)
6
DBA (data block start address register)
8
DBL (data block length register)
9
ACCU-3-H
10
ACCU-3-L
11
ACCU-4-H
12
ACCU-4-L
1)
Loading the contents of an addressed memory register into register
’0’or ’1 overwrites the address stored in ACCU 1.
Registers 4, 7, 13, 14 and 15 do not exist on the CPU 928B. LIR/TIR
operations with these register numbers are treated as no operations
(NOP).
LIR and TIR with the page
area
The LIR and TIR operations are not suitable for accessing the page
area (addresses F400 to FBFF) in the S5-135U multiprocessor PLC.
Use instead the operations from Section 9.4.4 "Accessing the Page
Memory" or the special functions from Section 6.21 "Page Accesses".
LIR/TIR: with 8-bit
memory areas
If you use the LIR and TIR operations to access memory areas that are
only 8 bits wide i.e., for memory addresses from E400 to E7FF and
≥ EE00 remember that
•• the TIR operation transfers only the low byte of the register. The
high byte of the register is lost.
and
•• the LIR operation overwrites the high byte of the registers with
FFH.
Table 9-2 16-bit register for LIR/TIR
9
Access using the Address in ACCU 1
CPU 928B Programming Guide
C79000-B8576-C898-01
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