Technical data

Figures 9-3 and 9-4 illustrate the difference between LIR/TIR access
to word and byte-oriented areas:
15 0
15
0
15 0
ACCU 1
ACCU 1
Register n
Register n
addressed
memory cell
addressed
memory cell
15
0
LIR n
TIR n
15 0
Fig. 9-3 LIR/TIR with 16-bit memory areas (word-oriented)
15 0
15
0
15 0
ACCU 1
ACCU 1
Register
n
Register
n
addressed
memory cell
addressed
memory cell
15
0
LIR n
FF
xx
TIR n
7
0
Fig. 9-4 LIR/TIR with a-bit memory areas (byte-oriented)
Access using the Address in ACCU 1
CPU 928B Programming Guide
9 - 10 C79000-B8576-C898-01