Technical data

Registers 0 to 3 and 9 to 12:
ACCU 1, 2, 3 and 4
During program execution, the CPU uses the accumulators as buffers.
Using the TIR operation, you can transfer the contents of the
accumulators into memory cells with absolute addresses. With the
LIR operation, you can load the contents of memory cells with
absolute addresses into the accumulators. The absolute address of the
memory cell is always in ACCU-1-L.
Examples
Register 6: Data Block Start
Address (DBA)
When you open a data block with the operations C DB and CX DX,
the address of DW 0 of this data block is loaded in register 6. The
block address list in DB 0 contains this address.
The DBA register is set to "0" before each OB 1 or FB 0 call.
The DBA register
remains the same if the following occurs:
•• a jump operation (JU/JC) causes program execution to continue in
a different block
or
•• a different program processing level is inserted.
You want to load the contents of the memory cell with the address A000
into flag word FW 100.
:L KH A000 load address A000 of the memory cell into ACCU 1
:LIR 1 load the contents of the memory cell in ACCU 1 into
: register 1 = load ACCU 1
:T FW 100 store the contents of address A000 in flag word FW 100
:BE
You want to transfer the contents of flag word 200 to the memory cell
with the address A000.
:L FW 200 load flag word FW 200 into ACCU 1
:L KH A000 load address A000, the destination address,
: in ACCU 1 (flag word FW 200 to ACCU 2)
:TIR 3 transfer contents of register 3 = ACCU 2 into
: the memory cell addressed by ACCU 1
:BE
9
Access using the Address in ACCU 1
CPU 928B Programming Guide
C79000-B8576-C898-01
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