Technical data

TNB and TWN between 8 and
16 bit memory areas
70
Addresses
in
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Source/
destination
Transfer of bytes 1 to 5:
Transfer of bytes 1 to 4:
L <source address>
L <destination address>
TNB 5
L <source address>
L <destination address>
TNW 2
15 7 0
Addresses
in ascending
Destination/source
address
Byte 4
Byte 2
Byte 5
Byte 3
Byte 1
8
ascending
order
address
order
Fig. 9-8 Transferring blocks of memory
Transferring Fields of Memory
CPU 928B Programming Guide
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