Technical data

Load and transfer
operations for the global
memory organized
in bytes
Operation Operand Description
LY GB
LY GW
LY GD
TY GB
TY GW
TY GD
-32768 to
+32767
-32768 to
+32767
-32768 to
+32767
-32768 to
+32767
-32768 to
+32767
-32768 to
+32767
add the specified constant to content
of the BR register and load the byte
addressed in this way in
ACCU-1-LL
1) 3)
add the specified constant to content
of the BR register and load the word
addressed in this way in ACCU-1-L
2) 3)
add the specified constant to content
of the BR register and load the double
word addressed in this way in ACCU 1
3)
add the specified constant to content
of the BR register and transfer the
content of ACCU-1-LL to the byte
addressed in this way
add the specified constant to content
of the BR register and transfer the
content of ACCU-1-L to the word
addressed in this way
add the specified constant to content
of the BR register and transfer the
content of ACCU 1 to the double
word addressed in this way
1)
ACCU-1-LH and ACCU-1-H are set to ’0’.
2)
ACCU-1-H is set to ’0’.
3)
ACCU 2
new
: = ACCU 1
old
Permissible address area The absolute address must be as follows:
•• between 0 and EFFFH (for LY GB, TY GB)
•• between 0 and EFFEH (for LY GW, TY GW)
•• between 0 and EFFCH (for LY GD, TY GD)
Table 9-8 Operations for access to the global memory organized in bytes
9
Operations with the Base Address Register (BR Register)
CPU 928B Programming Guide
C79000-B8576-C898-01
9 - 31