Technical data

Fig. 9-7 Occupation of the accumulators during the program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 17
Fig. 9-8 Transferring blocks of memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 20
Fig. 9-9 Function block for transferring blocks of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 21
Fig. 9-10 Loading the BR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 26
Fig. 9-11 Register - register transfer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 28
Fig. 10-1 Transferring IPC flags in the multiprocessor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 6
Fig. 10-2 Example of IPC flag areas on the CPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 7
Fig. 10-3 PG screen form for generating DB 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 10
Fig. 10-4 Sender/receiver identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 14
Fig. 10-5 Example of the occupation of the COR buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 17
Fig. 10-6 Overview of the blocks required in each CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 69
Fig. 10-7 Data exchange between 3 CPUs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 75
Fig. 11-1 Sequence of "program test" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 14
Fig. 11-2 Using the second interface as a PG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 20
Fig. 11-3 First example of a configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 21
Fig. 11-4 Second example of a configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 21
Fig. 11-5 Handling simultaneous jobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 24
Fig. 11-6 Typical sequence of a cyclic function and parallel short-running function. . . . . . . . . 11 - 25
Fig. 11-7 Sequence of two parallel cyclic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 27
Fig. 11-8 Sequence when a function blocks the CPU 928B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 28
List of Tables and Figures
CPU 928B Programming Guide
14 - 20 C79000-T8576-C898-01