Specifications

ST900 Family General Handbook
667/HB/32900/000 Issue 11 Page 111 of 265
as faulty, the DFM indicator is illuminated and the detector input forced active
(regardless of the setting of the DFM forcing action command ‘DFA’).
* Note that for the input to be seen inactive at the 200ms processing rate, all ten
20ms samples must have been inactive.
Thereafter, the force is only removed after 5 consecutive tests of the detector have
passed, but the fault log entry remains set and the DFM indicator remains
illuminated, until RFL=1 is entered.
If the maintenance engineer enters RFL=1, the controller will automatically perform
a test. If a kerbside detector which was reported as faulty passes this test, even if
this is the first test that it has passed, the fault log entry for that detector is cleared
and the detector is assumed to be working. This means that when the maintenance
engineer fixes a kerbside detector, they do not have to wait for 5 automatic tests
before they can clear the fault, they just need to enter RFL=1.
7.5 Operation during Certain Modes
This section describes the operation of demands and extensions during modes
other than ‘vehicle actuated’.
Note that regardless of the current mode, the controller continues to process
demand and extension inputs, even if those demands and extensions are being
ignored by the current mode. Thus, when the mode returns to ‘vehicle actuated’ for
example, the demands and extensions can immediately take effect.
7.5.1 Manual, Fixed Time and Start Up Mode
During Manual and Fixed Time Mode demands and extensions are disregarded.
This does not apply when Fixed Time to Current Maximums is the operative mode,
see section 23.2.
However, demands are inserted for all non-running real phases when these modes
terminate. Pedestrian phase WAIT indicators will be illuminated while a demand is
present. The actual phases to be demanded can be configured.
7.5.2 UTC
For UTC it is possible to configure the following (see section 15 for more
information):
1. Which phases and/or stages have latched or unlatched demands inserted
when a certain UTC demand bit is applied.
2. Which phases are extended by which UTC demand bits.
3. Demand dependent force bits and, for each force bit, which demands are to
be considered.