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Edition 04.98 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1998 All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics.
C515 User’s Manual Revision History : 04.98 Previous Releases: 08.97 Page (new version) Page (prev.
General Information C515 Table of Contents Page 1 1.1 1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 2 2.1 2.2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Information C515 Table of Contents Page 6.2.1.4 6.2.1.5 6.2.2 6.2.2.1 6.2.2.2 6.2.2.3 6.2.2.3.1 6.2.2.3.2 6.2.2.3.3 6.2.2.4 6.2.2.5 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.3.3.2 6.3.3.3 6.3.3.3.1 6.3.3.3.2 6.3.4 6.3.5 6.3.6 6.4 6.4.1 6.4.2 6.4.2.1 6.4.2.2 6.4.2.3 6.4.2.4 6.4.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Information C515 Table of Contents Page 8.1.2.2 8.1.3 8.1.4 8.1.5 The Second Possibility of Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . .8-1 Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 WDT Control and Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 9 9.1 9.
Introduction C515 1 Introduction The C515 is a member of the Siemens C500 family of 8-bit microcontrollers. lt is functionally fully upward compatible with the SAB-80C515/80C535 microcontrollers. The C515 basically operates with internal and/or external program memory. The C515-L is identical to the C515-1R, except that it lacks the on-chip porgram memory. Therefore, in this documentation the term C515 refers to all versions within this specification unless otherwise noted.
Introduction C515 Listed below is a summary of the main features of the C515: ¥ Full upward compatibility with SAB 80C515 ¥ Up to 24 MHz external operating frequency – 500 ns instruction cycle at 24 MHz operation ¥ 8K byte on-chip ROM (with optional ROM protection) – alternatively up to 64K byte external program memory ¥ Up to 64K byte external data memory ¥ 256 byte on-chip RAM ¥ On-chip emulation support logic (Enhanced Hooks Technology TM) ¥ Six 8-bit parallel I/O ports ¥ One input port for analog/digit
Introduction C515 VCC VSS Port 0 8 Bit Digital I/O XTAL1 XTAL2 Port 1 8 Bit Digital I/O ALE PSEN EA RESET PE/SWD Port 2 8 Bit Digital I/O Port 3 8 Bit Digital I/O C515 Port 4 8 Bit Digital I/O Port 5 8 Bit Digital I/O VAREF VAGND Port 6 8 Bit Analog/ Digital Input MCL03199 Figure 1-2 Logic Symbol Semiconductor Group 1-3
Introduction C515 1.1 Pin Configurations P4.7 P4.6 P4.5 P4.4 P4.3 PE/SWD P4.2 P4.1 P4.0 V CC P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 This section describes the pin configuration of the C515. 9 RESET VAREF VAGND P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 1 68 10 61 60 C515-LN/1RN 26 44 43 WR/P3.6 RD/P3.7 T2/P1.7 CLKOUT/P1.6 T2EX/P1.5 INT2/P1.4 CC3/INT6/P1.3 CC2/INT5/P1.2 CC1/INT4/P1.1 CC0/INT3/P1.0 VCC VSS XTAL2 XTAL1 P2.0 P2.1 P2.
P5.7 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 N.C. N.C. EA ALE PSEN N.C. P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 Introduction C515 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 N.C. VCC N.C. N.C. P4.0 P4.1 P4.2 PE/SWD P4.3 P4.4 P4.5 P4.6 P4.7 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 C515 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 N.C. VSS VCC N.
Introduction C515 1.2 Pin Definitions and Functions This section describes all external signals of the C515 with its function. Table 1-1 Pin Definitions and Functions Symbol Pin Number P-LCC68 Pin I/O*) Function Number P-MQFP80 P4.0-P4.7 1-3, 5-9 72-74, 76-80 I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs.
Introduction C515 Table 1-1 Pin Definitions and Functions (cont’d) Symbol P3.0-P3.7 Pin Number P-LCC68 Pin I/O*) Function Number P-MQFP80 21-28 15-22 21 15 22 16 23 17 24 18 25 26 27 19 20 21 28 22 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
Introduction C515 Table 1-1 Pin Definitions and Functions (cont’d) Symbol P1.0 - P1.7 Pin Number P-LCC68 Pin I/O*) Function Number P-MQFP80 36-29 31-24 36 31 35 30 34 29 33 28 32 31 27 26 30 29 25 24 I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
Introduction C515 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC68 Pin I/O*) Function Number P-MQFP80 XTAL2 39 36 – XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.
Introduction C515 Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC68 Pin I/O*) Function Number P-MQFP80 ALE 50 48 O The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access.
Fundamental Structure C515 2 Fundamental Structure The C515 is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C515 incorporates a 8-bit A/D converter, a timer 2 with capture/compare functions, as well as some enhancements in the Fail Save Mechanism unit. Figure 2-1 shows a block diagram of the C515.
Fundamental Structure C515 2.1 CPU The C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 12 MHz external clock, 58% of the instructions execute in 1.0 ms (24 MHz 500 ns).
Fundamental Structure C515 Special Function Register PSW (Address D0H) Reset Value : 00H Bit No. MSB D0H LSB D7H D6H D5H D4H D3H D2H D1H D0H CY AC F0 RS1 RS0 OV F1 P Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks.
Fundamental Structure C515 2.2 CPU Timing A machine cycle of the C515 consists of 6 states (12 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 12 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2.
Fundamental Structure C515 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 OSC (XTAL1) ALE Read Opcode S1 a) 1-Byte, S2 Read next Opcode (Discard) S3 S4 S6 1-Cycle Instruction, e.g. INC A Read 2nd Byte Read Opcode S1 b) 2-Byte, S5 Read next Opcode again S2 S3 S4 S5 Read next Opcode S6 1-Cycle Instruction, e.g.
Memory Organization C515 3 Memory Organization The C515 CPU manipulates operands in the following four address spaces: – – – – up to 64 Kbyte of program memory (8K on-chip program memory for C515-1R) up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C515.
Memory Organization C515 3.1 Program Memory, "Code Space" The C515-1R has 8 Kbytes of read-only program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C515-1R executes program code out of the internal ROM unless the program counter address exceeds 1FFFH. Address locations 2000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C515 fetches all instructions from the external 64K byte program memory. 3.
Memory Organization C515 3.5 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 43 special function registers (SFRs) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
Memory Organization C515 Table 3-1 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL PSW SP SYSCON SYSCON4) Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System Control Register System Control Register E0H 1) F0H 1) 83H 82H D0H 1) 81H B1H B1H 00H 00H 00H 00H 00H 07H XX1X XXXXB3) XXXX XXXXB3) A/D Converter Control Register A/D Converter Data Register A/D Converter Program
Memory Organization C515 Table 3-1 Special Function Registers - Functional Blocks (cont’d) Block Ports Serial Channel Symbol Name Address Contents after Reset TL2 T2CON 2) P0 P1 P2 P3 P4 P5 P6 Timer 2, Low Byte Timer 2 Control Register Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6, Analog/Digital Input CCH C8H 1) 80H 1) 90H 1) A0H 1) B0H 1 E8H 1) F8H 1) DBH 00H 00H FFH FFH FFH FFH FFH FFH – ADCON 2) PCON 2) SBUF SCON 2) A/D Converter Control Register Power Control Register Serial Channel Buff
Memory Organization C515 Table 3-2 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 2) P0 81H SP FFH 07H .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 82H 83H DPL 00H 00H .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .
Memory Organization C515 Table 3-2 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0H2) IRCON C1H CCEN 00H 00H EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC C2H C3H CCL1 00H 00H .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 C4H C5H CCL2 00H 00H .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 C6H C7H CCL3 00H 00H .7 .6 .5 .4 .3 .2 .1 .0 .
External Bus Interface C515 4 External Bus Interface The C515 allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception : if the C515 is used in systems with no external memory the generation of the ALE signal can be suppressed. Resetting bit EALE in SFR SYSCON register, the ALE signal will be gated off. This feature reduces RFI emissions of the system. 4.
External Bus Interface C515 a) One Machine Cycle S1 S2 S3 S4 S5 One Machine Cycle S6 S1 S2 S3 S4 S5 S6 ALE PSEN (A) without MOVX RD P0 PCH OUT PCH OUT P2 PCL OUT INST. IN INST. IN PCL OUT valid b) PCH OUT INST. IN PCL OUT PCL OUT valid S2 S3 S4 S5 INST. IN PCL OUT PCL OUT valid One Machine Cycle S1 PCH OUT INST. IN PCL OUT PCL OUT valid One Machine Cycle S6 S1 S2 S3 S4 S5 S6 ALE PSEN (B) with MOVX RD PCH OUT P2 P0 INST.
External Bus Interface C515 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated.
External Bus Interface C515 4.4 ALE, Address Latch Enable The C515 allows to switch off the ALE output signal. If the internal ROM is used (EA=1 and PC £ 1FFFH) and ALE is switched off by EALE=0, then, ALE will only go active during external data memory accesses (MOVX instructions). If EA=0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset the ALE generation is enabled. Special Function Register SYSCON (Address B1H) Bit No.
External Bus Interface C515 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation.
External Bus Interface C515 4.6 ROM Protection for the C515 The C515-1R allows to protect the contents of the internal ROM against unauthorized read out. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C515-1R version has to define whether ROM protection has to be selected or not. The C515-1R devices, which operate from internal ROM, are always checked for correct ROM contents during production test.
External Bus Interface C515 4.6.2 Protected ROM Mode ~ ~ ~ ~ If the ROM is protected, the ROM verification mode 2 as shown in figure 4-4 is used to verify the contents of the ROM. The detailed timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 10). RESET ~ ~ 1. ALE Pulse after Reset ~ ~ Data for Addr. 0 Latch Data for Addr. X-16-1 ~ ~ Data for Addr. 1 ~ ~ ~ ~ Port 0 Latch ~ ~ ~ ~ Latch ~ ~ ALE 12 t CLCL 6 t CLCL P3.
External Bus Interface C515 condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail and high for pass) during the 16 bytes are checked. In ROM verification mode 2, the C515 must be provided with a system clock at the XTAL pins.
Reset / System Clock C515 5 Reset and System Clock Operation 5.1 Hardware Reset Operation The hardware reset function incorporated in the C515 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated.
Reset / System Clock C515 The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 mF. The same considerations apply if the reset signal is generated externally (figure 5-1 b).
Reset / System Clock C515 5.2 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (low level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e.
Reset / System Clock C515 5.3 Oscillator and Clock Circuit XTAL1 and XTAL2 are the output and input of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-3 shows the recommended oscillator circuit.
Reset / System Clock C515 To Internal Timing Circuitry C515 XTAL1 XTAL2 1) C1 1) C2 Crystal or Ceramic Resonator MCS03226 Figure 5-4 On-Chip Oscillator Circuitry To drive the C515 with an external clock source, the external clock signal has to be applied to XTAL2, as shown in figure 5-5. XTAL1 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL2. VCC C515 N.C.
Reset / System Clock C515 5.4 System Clock Output For peripheral devices requiring a system clock, the C515 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON), a clock signal with 1/12 of the oscillator frequency is gated to pin P1.6/CLKOUT. To use this function the port pin must be programmed to a one (1), which is also the default after reset.
Reset / System Clock C515 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 ALE PSEN RD,WR CLKOUT MCT01858 Figure 5-6 Timing Diagram - System Clock Output Semiconductor Group 5-7
On-Chip Peripheral Components C515 6 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C515 except for the integrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O The C515 has six 8-bit I/O ports and one 8-bit input port for analog/digital input. Port 0 is an opendrain bidirectional I/O port, while ports 1 to 5 are quasi-bidirectional I/O ports with internal pullup resistors.
On-Chip Peripheral Components C515 Table 6-1 Alternate Functions of Port 1 and 3 Port Alternate Functions Description P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.
On-Chip Peripheral Components C515 6.1.2 Standard I/O Port Circuitry Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the six I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU.
On-Chip Peripheral Components C515 The output drivers of port 1 to 5 have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-2: Q=0), which turns off the output driver FET n1. Then, for ports 1 to 5 the pin is pulled high by the internal pullups, but can be pulled low by an external source.
On-Chip Peripheral Components C515 6.1.2.1 Port 0 Circuitry Port 0, in contrast to ports 1 to 4, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-3) is used only when the port is emitting 1’s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines.
On-Chip Peripheral Components C515 6.1.2.2 Port 1, Port 3 to Port 5 Circuitry The pins of ports 1, 3, 4, and 5 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-1. Figure 6-4 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open.
On-Chip Peripheral Components C515 6.1.2.3 Port 2 Circuitry As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter.
On-Chip Peripheral Components C515 Addr. Control VCC Q <_ 1 MUX Delay <_ 1 p1 p2 p3 1 State Port Pin =1 n1 VSS =1 Input Data (Read Pin) =1 MCS03229 Figure 6-6 Port 2 Pull-up Arrangement Port 2 in I/O function works similar to the standard port driver circuitry (section 6.1.2.4) whereas in address output function it works similar to Port 0 circuitry.
On-Chip Peripheral Components C515 6.1.2.4 Detailed Output Driver Circuitry In fact, the pullups mentioned before and included in figure 6-2, 6-4 and 6-5 are pullup arrangements. Figure 6-7 shows the detailed output driver (pullup arrangement) circuit of the the port 1 and 3 to 5 port lines. The basic circuitry of these ports is shown in figure 6-4.
On-Chip Peripheral Components C515 – The pullup FET p3 is of p-channel type. It is only activated if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high level shall be output at the pin (and the voltage is not forced lower than approximately 1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g when used as input.
On-Chip Peripheral Components C515 6.1.3 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1).
On-Chip Peripheral Components C515 6.1.4 Port Loading and Interfacing The output buffers of ports 1 to 5 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be be looked up in the DC characteristics in the Data Sheet of the C515 or in chapter 10 of this User’s Manual. The corresponding parameters are VOL and VOH. The same applies to port 0 output buffers.
On-Chip Peripheral Components C515 6.1.5 Read-Modify-Write Feature of Ports 0 to 5 Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in table 6-2. If the destination is a port or a port pin, these instructions read the latch rather than the pin.
On-Chip Peripheral Components C515 6.2 Timers/Counters The C515 contains three general purpose 16-bit timers/counters, timer 0, 1, and 2, which are useful in many applications for timing and counting. In "timer" function, the timer register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the counter rate is 1/12 of the oscillator frequency.
On-Chip Peripheral Components C515 6.2.1.1 Timer/Counter 0 and 1 Registers Totally six special function registers control the timer/counter 0 and 1 operation : – TL0/TH0 and TL1/TH1 - counter registers, low and high part – TCON and TMOD - control and mode select registers Special Function Register TL0 (Address 8AH) Special Function Register TH0 (Address 8CH) Special Function Register TL1 (Address 8BH) Special Function Register TH1 (Address 8DH) Bit No. MSB 7 6 5 4 3 2 1 LSB 0 8AH .7 .6 .5 .
On-Chip Peripheral Components C515 Special Function Register TCON (Address 88H) Bit No. 88H MSB 7 Reset Value : 00H LSB 0 6 5 4 3 2 1 8FH 8EH 8DH 8CH 8BH 8AH 89H 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 The shaded bits are not used in controlling timer/counter 0 and 1. Bit Function TR0 Timer 0 run control bit Set/cleared by software to turn timer/counter 0 ON/OFF. TF0 Timer 0 overflow flag Set by hardware on timer/counter overflow.
On-Chip Peripheral Components C515 Special Function Register TMOD (Address 89H) Bit No. MSB 7 89H Gate 6 5 4 C/T M1 M0 Reset Value : 00H 3 Timer 1 Control Gate 2 1 C/T M1 LSB 0 M0 TMOD Timer 0 Control Bit Function GATE Gating control When set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx" control bit is set. When cleared timer "x" is enabled whenever "TRx" control bit is set.
On-Chip Peripheral Components C515 6.2.1.2 Mode 0 Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by32 prescaler. Figure 6-9 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt.
On-Chip Peripheral Components C515 6.2.1.3 Mode 1 Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure 6-10. OSC ÷ 12 C/T = 0 C/T = 1 P3.4/T0 Control Gate TR0 =1 & <_ 1 P3.2/INTO MCS02095 P3.
On-Chip Peripheral Components C515 6.2.1.4 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 6-11. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. P3.
On-Chip Peripheral Components C515 6.2.1.5 Mode 3 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperate counters. The logic for mode 3 on timer 0 is shown in figure 6-12. TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1.
On-Chip Peripheral Components C515 6.2.2 Timer/Counter 2 with Additional Compare/Capture/Reload The timer 2 with additional compare/capture/reload features is one of the most powerful peripheral units of the C515. lt can be used for all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. Timer 2 is designed to support various automotive control applications (ignition/injection-control, anti-lock-brake ...
On-Chip Peripheral Components C515 P1.5/ T2EX Sync. EXF2 T2I0 T2I1 P1.7/ T2 <_ 1 Interrupt Request EXEN2 Sync. & Reload ÷ 12 OSC Reload f OSC ÷ 24 Timer 2 TL2 TH2 T2PS TF2 Compare 16 Bit Comparator 16 Bit Comparator 16 Bit Comparator P1.0/ INT3/ CC0 16 Bit Comparator Capture CCL3/CCH3 CCL2/CCH2 CCL1/CCH1 CRCL/CRCH Input/ Output Control P1.1/ INT4/ CC1 P1.2/ INT5/ CC2 P1.
On-Chip Peripheral Components C515 6.2.2.1 Timer 2 Registers This chapter describes all timer 2 related special function registers of timer 2. The interrupt related SFRs are also included in this section. Table 6-4 summarizes all timer 2 SFRs.
On-Chip Peripheral Components C515 The T2CON timer 2 control register is a bitaddressable register which controls the timer 2 function and the compare mode of registers CRC, CC1 to CC3. Special Function Register T2CON (Address C8H) Bit No. MSB 7 C8H Reset Value : 00H LSB 0 6 5 4 3 2 1 CFH CEH CDH CCH CBH CAH C9H C8H T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 T2CON The shaded bit is not used in controlling timer/counter 2.
On-Chip Peripheral Components C515 Special Function Register TL2 (Address CCH) Special Function Register TH2 (Address CDH) Special Function Register CRCL (Address CAH) Special Function Register CRCH (Address CBH) Bit No. Reset Value : 00H Reset Value : 00H Reset Value : 00H Reset Value : 00H MSB 7 6 5 4 3 2 1 LSB 0 CCH .7 .6 .5 .4 .3 .2 .1 LSB TL2 CDH MSB .6 .5 .4 .3 .2 .1 .0 TH2 CAH .7 .6 .5 .4 .3 .2 .1 LSB CRCL CBH MSB .6 .5 .4 .3 .2 .1 .
On-Chip Peripheral Components C515 Special Function Register IEN0 (Address A8H) Special Function Register IEN1 (Address B8H) Special Function Register IRCON (Address C0H) Bit No. MSB AFH A8H EAL Bit No. B8H BFH AEH WDT BEH ADH ACH ET2 ES BDH BCH EXEN2 SWDT EX6 C6H C5H Bit No.
On-Chip Peripheral Components C515 Special Function Register CCEN (Address C1H) Bit No. C1H MSB 7 6 5 4 Reset Value : 00H 3 Function COCAH3 COCAL3 Compare/capture mode for CC register 3 COCAH1 COCAL1 COCAH0 COCAL0 1 COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAH0 COCAL0 Bit COCAH2 COCAL2 2 LSB 0 CCEN COCAH3 COCAL3 Function 0 0 Compare/capture disabled 0 1 Capture on rising edge at pin P1.
On-Chip Peripheral Components C515 6.2.2.2 Timer 2 Operation The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. The detailed operation is described below. Timer Mode In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.
On-Chip Peripheral Components C515 Reload of Timer 2 The reload mode for timer 2 is selected by bits T2R0 and T2R1 in SFR T2CON. Figure 6-14 shows the configuration of timer 2 in reload mode. Mode 0 : When timer 2 rolls over from all l’s to all 0’s, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. The reload will happen in the same machine cycle in which TF2 is set, thus overwriting the count value 0000H.
On-Chip Peripheral Components C515 6.2.2.3 Compare Function of Registers CRC, CC1 to CC3 The compare function of a timer/register combination can be described as follows. The 16-bit value stored in a compare/capture register is compared with the contents of the timer register. lf the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin, and an interrupt is requested.
On-Chip Peripheral Components C515 Port Circuit Read Latch VCC Compare Register Circuit Compare Reg.
On-Chip Peripheral Components C515 Timer Count = FFFF H ~ ~ ~ ~ Contents of Timer 2 Timer Count = Compare Value Timer Count = Reload Value Interrupt can be generated on overflow Compare Output (P1.x/CCx) MCT01906 Interrupt can be generated on compare-match Figure 6-17 Function of Compare Mode 0 6.2.2.3.2 Modulation Range in Compare Mode 0 Generally it can be said that for every PWM generation in compare mode 0 with n-bit wide compare registers there are 2n different settings for the duty cycle.
On-Chip Peripheral Components C515 a) CCHx/CCLx = 0000 or H = CRCH/CRCL (maximum duty cycle) P1.x H L Appr. 1/2 Machine Cycle b) CCHx/CCLx = FFFF H (minimum duty cycle) Appr. 1/2 Machine Cycle P1.x H L MCT01907 Figure 6-18 Modulation Range of a PWM Signal, generated with a Timer 2/CCx Register Combination in Compare Mode 0* The following example shows how to calculate the modulation range for a PWM signal. To calculate with reasonable numbers, a reduction of the resolution to 8-bit is used.
On-Chip Peripheral Components C515 6.2.2.3.3 Compare Mode 1 In compare mode 1, the software adaptively determines the transition of the output signal. lt is commonly used when output signals are not related to a constant signal perlod (as in a standard PWM Generation) but must be controlled very precisely with high resolution and without jitter. In compare mode 1, both transitions of a signal can be controlled.
On-Chip Peripheral Components C515 Port Circuit Read Latch VCC Compare Register Circuit Compare Reg.
On-Chip Peripheral Components C515 6.2.2.4 Using Interrupts in Combination with the Compare Function The compare service of registers CRC, CC1, CC2 and CC3 is assigned to alternate output functions at port pins P1.0 to P1.3. Another option of these pins is that they can be used as external interrupt inputs. However, when using the port lines as compare outputs then the input line from the port pin to the interrupt system is disconnected (but the pin’s level can still be read under software control).
On-Chip Peripheral Components C515 The second configuration which should be noted is when compare function is combined with negative transition activated interrupts. lf the port latch of port P1.0 contains a 1, the interrupt request flags IEX3 will immediately be set after enabling the compare mode for the CRC register. The reason is that first the external interrupt input is controlled by the pin’s level.
On-Chip Peripheral Components C515 6.2.2.5 Capture Function Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this function. In mode 0, an external event latches the timer 2 contents to a dedicated capture register. In mode 1, a capture will occur upon writing to the low order byte of the dedicated 16-bit capture register.
On-Chip Peripheral Components C515 Input Clock TL2 TH2 TF2 Timer 2 Interrupt Request IEX3 External Interrupt 3 Request "Write to CRCL" Mode 1 P1.0/INT 3/ CC0 Capture Mode 0 T2 CON.6 CRCL CRCH MCS01909 Figure 6-21 Timer 2 - Capture with Register CRC Input Clock TL2 TH2 TF2 Timer 2 Interrupt Request IEX4 External Interrupt 4 Request "Write to CCL1" Mode 1 Capture Mode 0 CCL1 P1.
On-Chip Peripheral Components C515 6.3 Serial Interface The serial port of the C515 is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost).
On-Chip Peripheral Components C515 6.3.1 Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then a stop bit follows. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows.
On-Chip Peripheral Components C515 Special Function Register SCON (Address 98H) Special Function Register SBUF (Address 99H) Bit No.
On-Chip Peripheral Components C515 6.3.3 Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization.
On-Chip Peripheral Components C515 Timer 1 Overflow f OSC /2 SCON.7 SCON.6 (SM0/ SM1) ADCON.7 (BD) 0 1 ÷ 39 Mode 1 Mode 3 PCON.7 (SMOD) ÷2 0 1 Baud Rate Clock Mode 2 Mode 0 ÷6 Only one mode can be selected Note: The switch configuration shows the reset state. MCB03206 Figure 6-23 Baud Rate Generation for the Serial Port Depending on the programmed operating mode different paths are selected for the baud rate clock generation.
On-Chip Peripheral Components C515 6.3.3.3 Baud Rate in Mode 1 and 3 In these modes the baud rate is variable and can be generated alternatively by a baud rate generator with a fixed prescaler or by timer 1. 6.3.3.3.1 Using the Baud Rate Generator In modes 1 and 3, the C515 can use the internal baud rate generator for the serial port. To enable this feature, bit BD (bit 7 of special function register ADCON) must be set. This baud rate generator divides the oscillator frequency by 2 x 39=78.
On-Chip Peripheral Components C515 Table 6-5 Timer 1 generated Commonly used Baud Rates fOSC (MHz) Baud Rate SMOD BD Timer 1 Mode Reload Value Mode 1, 3: 62.5 Kbaud 125 Kbaud 19.5 Kbaud 9.6 Kbaud 4.8 Kbaud 2.4 Kbaud 1.2 Kbaud 110 Baud 110 Baud 4.8 Kbaud 9.6 Kbaud 6.4 Kbaud 12.8 Kbaud 9.6 Kbaud 19.2 Kbaud 12.0 24.0 11.059 11.059 11.059 11.059 11.059 6.0 12.0 12.0 12.0 16.0 16.0 24.0 24.
On-Chip Peripheral Components C515 6.3.4 Details about Mode 0 Serial data enters and exists through RXD. TXD outputs the shift clock. 8 data bits are transmitted/ received: (LSB first). The baud rate is fixed at fOSC/12. Figure 6-24 shows a simplified functional diagram of the serial port in mode 0. The associated timing is illustrated in figure 6-25. Transmission is initiated by any instruction that uses SBUF as a destination register.
On-Chip Peripheral Components C515 Internal Bus 1 Write to SBUF S Q & SBUF CLK Shift D Zero Detector Start Baud Baud Rate ClockRate S6 Shift TX Control TX Clock TI Clock RI Start Receive RX Control RX Clock 1 1 1 1 1 1 1 0 Shift Input Shift Register Shift Load SBUF SBUF Read SBUF Internal Bus MCS02101 Figure 6-24 Serial Interface, Mode 0, Functional Diagram Semiconductor Group <_ 1 Shift Clock & RI Send <_ 1 Serial Port Interrupt REN RXD P3.0 Alt. Output Function 6-49 RXD P3.
Semiconductor Group S6P2 Write to SBUF Figure 6-25 Serial Interface, Mode 0, Timing Diagram 6-50 TXD (Shift Clock) RXD (Data In) Write to SCON (Clear RI) D0 S3P1 S6P1 D0 S5P D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 MCT02102 Transmit Shift Receive RI TI TXD (Shift Clock) RXD (Data Out) Shift Send ALE SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS SSSSSS 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 On-Chip Peripheral Components C5
On-Chip Peripheral Components C515 6.3.5 Details about Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. The baud rate is determined either by the timer 1 overflow rate or by the internal baud rate generator. Figure 6-26 shows a simplified functional diagram of the serial port in mode 1. The associated timings for transmit/receive are illustrated in figure 6-27.
On-Chip Peripheral Components C515 Internal Bus 1 Write to SBUF S Q & SBUF D CLK Zero Detector Shift Start Data TX Control ÷ 16 TX Clock Send RI Load SBUF <_ 1 Serial Port Interrupt Baud Rate Clock TI ÷ 16 Sample 1-to-0 Transition Detector RX Start RX Control 1FFH Shift Bit Detector Input Shift Register (9Bits) RXD Shift Load SBUF SBUF Read SBUF Internal Bus MCS02103 Figure 6-26 Serial Interface, Mode 1, Functional Diagram Semiconductor Group 6-52 <_ 1 TXD
Semiconductor Group TI TXD Shift Data Send Figure 6-27 Serial Interface, Mode 1, Timing Diagram 6-53 Receive RI Shift Bit Detector Sample Times Start Bit S1P1 D1 Start Bit ÷ 16 Reset D0 D0 D2 D1 D3 D2 D4 D3 D5 D4 D6 D5 D7 D6 D7 Stop Bit MCT02104 Stop Bit Transmit RXD RX Clock Write to SBUF TX Clock On-Chip Peripheral Components C515
On-Chip Peripheral Components C515 6.3.6 Details about Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is generated by either using timer 1 or the internal baud rate generator.
On-Chip Peripheral Components C515 Internal Bus TB8 Write to SBUF S Q & SBUF D CLK Zero Detector Start ÷ 16 Stop Bit Shift Generation TX Control TX Clock Baud Rate Clock Data TI Send RI Load SBUF <_ 1 Serial Port Interrupt ÷ 16 Sample 1-to-0 Transition Detector RX Clock Start RX Control 1FF Bit Detector Shift Input Shift Register (9Bits) RXD Shift Load SBUF SBUF Read SBUF Internal Bus MCS02105 Figure 6-28 Serial Interface, Mode 2 and 3, Functional Diagram Semiconductor Group 6-55
Semiconductor Group Figure 6-29 Serial Interface, Mode 2 and 3, Timing Diagram 6-56 Receive RI Shift Sample Times Bit Detector ÷ 16 Reset Start Bit Start Bit RX Clock D0 Mode 2 : S6P1 Mode 3 : S1P1 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 TB8 RB8 Stop Bit MCT02587 Stop Bit Transmit RX Stop Bit Gen.
On-Chip Peripheral Components C515 6.
On-Chip Peripheral Components C515 Internal Bus IEN1 (B8 H ) EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC IEX6 IEX5 IEX4 IEX3 0 IADC _ BSY ADM MX2 MX1 MX0 IRCON (C0 H ) EXF2 TF2 ADCON (D8H ) BD CLK ADDAT (D9 H) Single/ Continuous Mode Port 6 MUX f OSC /2 S&H A/D Converter Conversion Clock f ADC ÷4 LBS .1 .2 .3 .4 .5 .6 MSB Input Clock f IN Start of Conversion Write to DAPR VINTAREF VINTAGND VAREF VAGND Internal Reference Voltages DAPR (DA H) .7 .6 .5 .
On-Chip Peripheral Components C515 6.4.2 A/D Converter Registers This section describes the bits/functions of the registers which are used by the A/D converter. – – – – ADCON (A/D converter control register) ADDAT (A/D converter data register) IEN1 and IRCON (A/D converter Interrupt control bits) DAPR (D/A converter program register) for the programmable reference voltages. 6.4.2.
On-Chip Peripheral Components C515 Note :Generally, before entering the power-down mode, an A/D conversion in progress must be stopped. If a single A/D conversion is running, it must be terminated by polling the BSY bit or waiting for the A/D conversion interrupt. In continuous conversion mode, bit ADM must be cleared and the last A/D conversion must be terminated before entering the power-down mode. A single A/D conversion is started by writing to SFR ADDAT with dummy data.
On-Chip Peripheral Components C515 6.4.2.3 A/D Converter Interrupt Control Bits in IEN1 and IRCON The A/D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON. Special Function Register IEN1 (Address B8H) Special Function Register IRCON (Address C0H) Bit No.
On-Chip Peripheral Components C515 6.4.2.4 Programmable Reference Voltages of the A/D Converter (DAPR Register) The C515 has two pins to which a reference voltage range for the on-chip A/D converter is applied (pin VAREF for the upper voltage and pin VAGND for the lower voltage).
On-Chip Peripheral Components C515 DAPR.3-.0 is the contents of the low-order nibble, and DAPR.7-.4 the contents of the high-order nibble of DAPR. If DAPR.3-.0 or DAPR.7-.4 = 0, the internal reference voltages correspond to the external reference voltages VAGND and VAREF, respectively. If VAINPUT > VIntAREF, the conversion result is FFH, if VAINPUT < VIntAGDN , the conversion result is 00H (VAINPUT is the analog input voltage).
On-Chip Peripheral Components C515 5.00 V VAREF AN0 AN1 AN.. 4.375 V 3.125 V 2.5 V VINTAREF 2.5 V 0.625 V 0V VAGND 1.25 V VINTAGND MCA01899 Figure 6-31 Adjusting the Internal Reference Voltages within Range of the External Analog Input Voltages 5.00 V VAREF First Conversion 20 mV Resolution Second Conversion 5 mV Resolution 3.125 V VINTAREF 1.
On-Chip Peripheral Components C515 The external reference voltage supply need only be applied when the A/D converter is used, otherwise the pins VAREF and VAGND may be left unconnected. The reference voltage supply has to meet some requirements concerning the level of VAGND and VAREF and the output impedance of the supply voltage (see also "A/D Converter Characteristics" in the data sheet). – The voltage VAREF must meet the following specification : VAREF = VCC + 0.
On-Chip Peripheral Components C515 6.4.3 A/D Conversion Timing An A/D conversion is internally started by writing the SFR DAPR. A write to SFR DAPR will start a new conversion even if a conversion is currently in progress. The conversion begins with the next machine cycle, and the BSY flag in SFR ADCON will be set. The A/D conversion procedure is divided into three parts : – Sample phase (tS), used for sampling the analog input voltage. – Conversion phase (tCO), used for the real A/D conversion.
On-Chip Peripheral Components C515 Start of an A/D Conversion BSY Bit Result is written into ADDAT Sample Phase tS Conversion Phase t CO t WR t ADCC A/D Conversion Time Cycle Time t WR = t IN t ADCC = t S + t CO = 40 t IN + 32 t IN = 72 t IN MOV ADDAT,#0 x with t IN = 2x t CLCL Write Result Cycle MOV A, ADDAT 1 Instruction Cycle 1 2 3 4 ~ ~ ~ ~ x-1 Write Result Phase 5 11 12 13 14 15 16 Start of next conversion (in continuous mode) t ADCC = 80 tIN ~ ~ Start of A/D conversion cycle
On-Chip Peripheral Components C515 An A/D conversion is always started with the beginning of a processor cycle when it has been initiated by writing SFR ADDAT. The ADDAT write operation may take one or two machine cycles. In figure 6-33, the instruction MOV ADDAT,#0 starts the A/D conversion (machine cycle X-1 and X). The total A/D conversion (sample and conversion phase) is finished with the beginning of the 14th machine cycle after the A/D conversion start.
Interrupt System C515 7 Interrupt System The C515 provides 12 interrupt sources with four priority levels. Five interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seven interrupts may be triggered externally (P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6). This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers.
Interrupt System C515 Highest Priority Level IT0 TCON.0 A/D Converter Timer 0 Overflow IADC IRCON.0 TF0 TCON.5 P1.4/ INT2 I2FR T2CON.5 P3.3/ INT1 IT1 TCON.2 P1.0/ INT3 CC0 IE0 TCON.1 I3FR T2CON.6 IEX2 IRCON.1 IE1 TCON.3 IEX3 IRCON.2 Bit addressable EX0 IEN0.0 0003 H EADC IEN1.0 0043 H Lowest Priority Level ET0 IEN0.1 000B H EX2 IEN1.1 004B H EX1 IEN0.2 0013 H EX3 IEN1.2 0053 H EAL IEN0.
Interrupt System C515 Highest Priority Level TF1 TCON.7 P1.1/ INT4 CC1 USART IEX4 IRCON.3 RI SCON.0 IEX5 IRCON.4 Timer 2 Overflow P1.5/ T2EX TF2 IRCON.6 EX4 IEN1.3 005B H Lowest Priority Level IEX6 IRCON.5 Bit addressable ES IEN0.4 0023 H EX5 IEN1.4 0063 H ET2 IEN0.5 002B H EX6 IEN1.5 006B H EAL IEN0.7 Request Flag is cleared by hardware Figure 7-2 Interrupt Structure, Overview Part 2 Semiconductor Group IP1.3 IP0.3 IP1.4 IP0.4 IP1.5 IP0.5 <_ 1 EXF2 EXEN2 IRCON.7 IEN1.7 P1.
Interrupt System C515 7.1 Interrupt Registers 7.1.1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 and IEN1. Register IEN0 also contains the global disable bit (EAL), which can be cleared to disable all interrupts at once. Generally, after reset all interrupt enable bits are set to 0. That means that the corresponding interrupts are disabled.
Interrupt System C515 The IEN1 register contains enable/disable flags of the timer 2 external timer reload interrupt, the external interrupts 2 to 6, and the A/D converter interrupt. Special Function Register IEN1 (Address B8H) Bit No. B8H MSB BFH BEH EXEN2 SWDT BDH EX6 BCH EX5 Reset Value : 00H BBH EX4 BAH B9H LSB B8H EX3 EX2 EADC IEN1 The shaded bit is not used for interrupt control.
Interrupt System C515 7.1.2 Interrupt Request / Control Flags Special Function Register TCON (Address 88H) Bit No. 88H MSB 8FH TF1 8EH TR1 8DH TF0 8CH TR0 Reset Value : 00H 8BH IE1 8AH 89H LSB 88H IT1 IE0 IT0 TCON The shaded bits are not used for interrupt control. Bit Function TF1 Timer 1 overflow flag Set by hardware on timer/counter 1 overflow. Cleared by hardware when processor vectors to interrupt routine. TF0 Timer 0 overflow flag Set by hardware on timer/counter 0 overflow.
Interrupt System C515 Special Function Register T2CON (Address C8H) Bit No. MSB CFH C8H T2PS CEH I3FR CDH I2FR CCH T2R1 CBH T2R0 Reset Value : 00H CAH C9H T2CM T2I1 LSB C8H T2I0 T2CON The shaded bits are not used for interrupt control. Bit Function I3FR External interrupt 3 rising/falling edge control flag If I3FR = 0, the external interrupt 3 is activated by a falling edge at P1.0/INT3/CC0. If I3FR = 1, the external interrupt 3 is activated by a rising edge at P1.0/INT3/CC0.
Interrupt System C515 Special Function Register IRCON (Address C0H) Bit No. MSB C7H C0H EXF2 C6H TF2 C5H IEX6 C4H IEX5 C3H IEX4 Reset Value : 00H C2H C1H LSB C0H IEX3 IEX2 IADC IRCON Bit Function EXF2 Timer 2 external reload flag EXF2 is set when a reload is caused by a falling edge on pin T2EX while EXEN2 = 1. If ET2 in IEN0 is set (timer 2 interrupt enabled), EXF2 = 1 will cause an interrupt. EXF2 can be used as an additional external interrupt when the reload function is not used.
Interrupt System C515 The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in register IRCON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared by software. The A/D converter interrupt is generated by IADC bit in register IRCON.
Interrupt System C515 Special Function Register SCON (Address. 98H) Bit No. MSB 9FH 98H SM0 9EH SM1 9DH SM2 9CH REN 9BH TB8 Reset Value : 00H 9AH 99H LSB 98H RB8 TI RI SCON The shaded bits are not used for interrupt control. Bit Function TI Serial interface transmitter interrupt flag Set by hardware at the end of a serial data transmission. Must be cleared by software. RI Serial interface receiver interrupt flag Set by hardware if a serial data byte has been received.
Interrupt System C515 7.1.3 Interrupt Priority Registers The lower six bits of these two registers are used to define the interrupt priority level of the interrupt groups as they are defined in table 7-1 in the next section. Special Function Register IP0 (Address A9H) Special Function Register IP1 (Address B9H) Bit No. MSB 7 Reset Value : X0000000B Reset Value : XX000000B 6 5 4 3 2 1 LSB 0 A9H – WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 Bit No. 7 6 5 4 3 2 1 0 B9H – – IP1.
Interrupt System C515 7.2 Interrupt Priority Level Structure The following table shows the interrupt grouping of the C515 interrupt sources.
Interrupt System C515 7.3 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1.
Interrupt System C515 Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7-3 then, in accordance with the above rules, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed. Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine.
Interrupt System C515 7.4 External Interrupts The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition activated by setting or clearing bit IT0, respectively in register TCON. If ITx = 0 (x = 0 or 1), external interrupt x is triggered by a detected low level at the INTx pin. If ITx = 1, external interrupt x is negative edge-triggered.
Interrupt System C515 a) Level-Activated Interrupt P3.x/INTx Low-Level Threshold > 1 Machine Cycle b) Transition-Activated Interrupt High-Level Threshold e.g. P3.
Interrupt System C515 7.5 Interrupt Response Time If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be next instruction to be executed. The call itself takes two cycles.
Fail Safe Mechanisms C515 8 Fail Safe Mechanisms 8.1 Watchdog Timer 8.1.1 General Operation As a means of graceful recovery from software or hardware upset a watchdog timer is provided in the C515. lf the software fails to clear the watchdog timer at least every 65532 ms (at 12 MHz clock rate), an internal hardware reset will be initiated. The software can be designed such that the watchdog times out if the program does not progress properly.
Fail Safe Mechanisms C515 8.1.3 Refreshing the Watchdog Timer Once started, the watchdog timer can only be cleared to 0000H by first setting bit WDT and with the next instruction setting bit SWDT. Bit WDT will automatically be cleared during the second machine cycle after having been set. For this reason, setting SWDT bit has to be a one cycle instruction (e.g. SETB SWDT). This double instruction clearing of the watchdog timer was implemented to minimize the chance of unintentionally clearing the watchdog.
Fail Safe Mechanisms C515 8.1.5 WDT Control and Status Flags The watchdog timer is controlled by two control flags (located in SFR IEN0 and IEN1) and one status flags (located in SFR IP0).
Power Saving Modes C515 9 Power Saving Modes The C515 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. All the power saving modes are initiated by software. 9.
Power Saving Modes C515 9.2 Power Saving Mode Control Register The functions of the power saving modes are controlled by bits which are located in the special function register PCON. The bits PDE, PDS and IDLE, IDLS located in SFR PCON select the power down mode or the idle mode, respectively. If the power down mode and the idle mode are set at the same time, power down takes precedence. Furthermore, register PCON contains two general purpose flags.
Power Saving Modes C515 9.3 Idle Mode In the idle mode the oscillator of the C515 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, and all timers with the exception of the watchdog timer are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode.
Power Saving Modes C515 The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and IDLS, does not initiate the idle mode. Bits IDLE and IDLS will automatically be cleared after being set. If one of these register bits is read the value that appears is 0.
Power Saving Modes C515 9.4 Slow Down Mode Operation (C515-LM/1RM only) In some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (e.g. if the controller is waiting for an input signal). Since in CMOS devices there is an almost linear dependence of the operating frequency and the power supply current, a reduction of the operating frequency results in reduced power consumption.
Power Saving Modes C515 9.5 Power Down Mode In the power down mode, the RC osciillator and the on-chip oscillator which operates with the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's.
Power Saving Modes C515 9.6 State of Pins in the Power Saving Modes In the idle mode and in the power down mode the port pins of the C515 have a well defined status which is listed in the following table 9-1. This state of some pins also depends on the location of the code memory (internal or external).
Device Specifications C515 10 Device Specifications 10.1 Absolute Maximum Ratings Ambient temperature under bias (TA) .............................................................. 0 ˚C to + 110 ˚C Storage temperature (TST) ...............................................................................– 65 ˚C to + 150 ˚C Voltage on VCC pins with respect to ground (VSS) ............................................– 0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS) ..........................
Device Specifications C515 10.2 DC Characteristics VCC = 5 V + 10%, – 15%; VSS = 0 V Parameter TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C Symbol for the SAB-C515 for the SAF-C515 for the SAH-C515 Limit Values min. max. 0.2 VCC - 0.1 0.2 VCC - 0.3 Input low voltages all except EA EA pin VIL VIL1 – 0.5 – 0.
Device Specifications C515 Power Supply Current Parameter Symbol Limit Values typ. 9) max. 10) Unit Test Condition Active mode 12 MHz 16 MHz 24 MHz ICC ICC ICC 11.0 13.7 19.1 14.8 18.2 25 mA mA mA 4) Idle mode 12 MHz 16 MHz 24 MHz ICC ICC ICC 5.8 6.9 9.1 8.1 9.6 12.8 mA mA mA 5) Active mode with slow-down enabled 12 MHz 16 MHz 24 MHz ICC ICC ICC 4.2 4.9 6.3 6.1 7.0 8.
Device Specifications C515 30 I CC max I CC typ mA I CC 25 Active Mode 20 Active Mode 15 Idle Mode 10 Idle Mode 5 Active Mode with Slow Down 0 0 4 8 12 Active mode : I CC typ = 0.68 x f OSC + 2.8 : I CC max = 0.85 x f OSC + 4.6 Idle mode : I CC typ = 0.28 x f OSC + 2.4 : I CC max = 0.39 x f OSC + 3.4 16 20 MHz f OSC 24 Active mode with slow-down : I CC typ = 0.18 x f OSC + 2.0 : I CC max = 0.23 x f OSC + 3.3 f OSC is the oscillator frequency in MHz. I CC values are given in mA.
Device Specifications C515 10.3 A/D Converter Characteristics VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C for the SAB-C515 for the SAF-C515 for the SAH-C515 VCC – 0.25 V £ VAREF £ VCC + 0.1 V ; VSS – 0.1 V £ VAGND £ VSS + 0.2 V; VIntAREF - VIntAGND ³ 1 V; Parameter Analog input voltage Symbol VAIN Limit Values min. max. VAGND - VAREF + 0.2 0.
Device Specifications C515 10.4 AC Characteristics (16 MHz) TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C VCC = 5 V + 10%, – 15%; VSS = 0 V for the SAB-C515 for the SAF-C515 for the SAH-C515 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 16 MHz Clock Unit Variable Clock 1/tCLCL = 1 MHz to 16 MHz min. max. min. max.
Device Specifications C515 AC Characteristics (16 MHz) (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values 16 MHz Clock Unit Variable Clock 1/tCLCL = 1 MHz to 16 MHz min. max. min. max.
Device Specifications C515 10.5 AC Characteristics (24 MHz) TA = 0 to 70 °C TA = – 40 to 85 °C TA = – 40 to 110 °C VCC = 5 V + 10%, – 15%; VSS = 0 V for the SAB-C515 for the SAF-C515 for the SAH-C515 (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 24 MHz Clock Unit Variable Clock 1/tCLCL = 1 MHz to 24 MHz min. max. min. max.
Device Specifications C515 AC Characteristics (24 MHz) (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values 24 MHz Clock Unit Variable Clock 1/tCLCL = 1 MHz to 24 MHz min. max. min. max.
Device Specifications C515 t LHLL ALE t AVLL t PLPH t LLPL t LLIV t PLIV PSEN t AZPL t PXAV t LLAX t PXIZ t PXIX Port 0 A0 - A7 Instr.
Device Specifications C515 t WHLH ALE PSEN t LLDV t LLWL t RLRH RD t RLDV t AVLL t RHDZ t LLAX2 t RLAZ Port 0 A0 - A7 from Ri or DPL t RHDX Data IN A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.
Device Specifications C515 t WHLH ALE PSEN t LLWL t WLWH WR t QVWX t AVLL t WHQX t LLAX2 Port 0 A0 - A7 from Ri or DPL t QVWH Data OUT A0 - A7 from PCL Instr.IN t AVWL Port 2 P2.0 - P2.
Device Specifications C515 t SLLH ALE t LLSH t SHSL t LLSH CLK OUT t SLSH PSEN RD,WR Program Memory Access Data Memory Access CLKOUT Timing t CLCL VCC- 0.5V 0.45V 0.7 VCC 0.2 VCC- 0.
Device Specifications C515 10.6 ROM Verification Characteristics for the C515-1R ROM Verification Mode 1 Parameter Symbol Address to valid data P1.0 - P1.7 P2.0 - P2.4 tAVQV Limit Values min. max. – 10 tCLCL Address New Address t AVQV Port 0 Data OUT Address : P1.0 - P1.7 = A0 - A7 P2.0 - P2.4 = A8 - A12 Data : P0.0 - P0.
Device Specifications C515 ROM Verification Mode 2 Parameter Symbol Limit Values Unit min. typ max. ALE pulse width tAWD – 2 tCLCL – ns ALE period tACY – 12 tCLCL – ns Data valid after ALE tDVA – – 4 tCLCL ns Data stable after ALE tDSA 8 tCLCL – – ns P3.5 setup to ALE low tAS – tCLCL – ns Oscillator frequency 1/ tCLCL 1 – 24 MHz t ACY t AWD ALE t DSA t DVA Port 0 Data Valid t AS P3.
Device Specifications C515 VCC -0.5 V 0.2 VCC+0.9 Test Points 0.2 VCC -0.1 0.45 V MCT00039 AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’. AC Testing: Input, Output Waveforms VOH -0.1 V VLoad +0.1 V Timing Reference Points VLoad VLoad -0.1 V VOL +0.
Device Specifications C515 10.7 Package Information (P-LCC-68) 5.08 max 1.2 x 45˚ 0.2 0.5 min 3.5 ±0.2 Plastic Package, P-LCC-68 (SMD) (Plastic Lead Chip-Carrier) 1.27 0.43 ±0.1 0.81 max 23.3 ±0.3 0.18 M A-B D 68x 20.32 24.21 ±0.07 1) 0.1 0.38 M A-B D 34x 25.28 -0.26 D B A 0.5 x 45˚ 3x 68 1 1.1 x 45˚ Index Marking 24.21 ±0.07 1) 25.28 -0.26 1) Does not include plastic or metal protrusions of 0.15 max per side Sorts of Packing Package outlines for tubes, trays etc.
Device Specifications C515 10.8 Package Information (P-MQFP-80) 0.65 0.3 ±0.08 H 7˚max 0.15 +0.08 -0.02 0.25 min 2 +0.1 -0.05 2.45 max Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) 0.88 C 0.1 12.35 0.12 17.2 0.2 A-B D 80x 0.2 A-B D H 4x 14 1) M A-B D C 80x D B 14 1) 17.2 A 0.6x45˚ 1) Does not include plastic or metal protrusions of 0.25 max per side Sorts of Packing Package outlines for tubes, trays etc.
Index C515 11 Index COCAH0 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAH1 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAH2 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAH3 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAL0 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAL1 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAL2 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 COCAL3 . . . . . . . . . . . . . . . . . . . . 3-7, 6-28 CPU Accumulator . . . . . . . . .
Index C515 Overlapping of data/program memory Program memory access . . . . . . . . . . Program/data memory timing . . . . . . PSEN signal . . . . . . . . . . . . . . . . . . . . Role of P0 and P2 . . . . . . . . . . . . . . . 4-3 4-3 4-2 4-3 4-1 External interrupts . . . . . . . . . . . . . . .7-15 Handling procedure . . . . . . . . . . . . . .7-13 Priority registers . . . . . . . . . . . . . . . .7-11 Priority within level structure . . . . . . .7-12 Request flags . . . . . . . . . . . . . .
Index C515 PDS . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2 Pin configuration . . . . . . . . . . . . . . . . . . 1-4 P-MQFP-80 package . . . . . . . . . . 1-4, 1-5 Pin definitions and functions . . . . . 1-6–1-10 Ports . . . . . . . . . . . . . . . . . . . . . . . 6-1–6-13 Alternate functions . . . . . . . . . . . . . . . 6-2 Loading and interfacing . . . . . . . . . . 6-12 Output driver circuitry . . . . . . . . . 6-9–6-10 Output/input sample timing . . . . . . .
Index C515 Timer/counter 0 and 1 . . . . . . . 6-14–6-21 Mode 0, 13-bit timer/counter . . . . 6-18 Mode 1, 16-bit timer/counter . . . . 6-19 Mode 2, 8-bit rel. timer/counter . . 6-20 Mode 3, two 8-bit timer/counter . . 6-21 Registers . . . . . . . . . . . . . . . 6-15–6-17 Timer/counter 2 . . . . . . . . . . . . 6-22–6-40 Alternate port functions . . . . . . . . 6-22 Block diagram . . . . . . . . . . . . . . . 6-23 Capture function . . . . . . . . . . 6-39–6-40 Compare function . . . . . . . . .
