Important Notes, Contents SIMATIC S7-200 Programmable Controller System Manual This manual has the order number: 6ES7298-8FA20-8BH0 Introducing the S7-200 Micro PLC Installing an S7-200 Micro PLC Getting Started with an S7-200 Programming System Basic Concepts for Programming an S7-200 CPU 1 CPU Memory: Data Types and Addressing Modes 5 CPU and Input/Output Configuration Setting Up Communications Hardware and Network Communications 6 Conventions for S7-200 Instructions 8 SIMATIC Instructions IEC
Safety Guidelines This manual contains notices which you should observe to ensure your own personal safety, as well as to protect the product and connected equipment. These notices are highlighted in the manual by a warning triangle and are marked as follows according to the level of danger: ! Danger indicates that death, severe personal injury, or substantial property damage will result if proper precautions are not taken.
Important Notes Purpose The S7-200 series is a line of micro-programmable logic controllers (Micro PLCs) that can control a variety of automation applications. Compact design, low cost, and a powerful instruction set make the S7-200 controllers a perfect solution for controlling small applications. The wide variety of CPU sizes and voltages, and the windows-based programming tool, give you the flexibility you need to solve your automation problems.
Important Notes Scope of the Manual The information contained in this manual pertains in particular to the following products: S7-200 CPU models: CPU 221, CPU 222, and CPU 224 STEP 7-Micro/WIN 32, version 3.
Important Notes How to Use This Manual If you are a first-time (novice) user of S7-200 Micro PLCs, you should read the entire S7-200 Programmable Controller System Manual. If you are an experienced user, refer to the manual table of contents or index to find specific information. The S7-200 Programmable Controller System Manual is organized according to the following topics: “Introducing the S7-200 Micro PLC” (Chapter 1) provides an overview of some of the features of the equipment.
Important Notes vi S7-200 Programmable Controller System Manual C79000-G7076-C233-01
Contents 1 2 3 4 Introducing the S7-200 Micro PLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Comparing the Features of the S7-200 Micro PLCs . . . . . . . . . . . . . . . . . . 1-2 1.2 Major Components of the S7-200 Micro PLC . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Installing an S7-200 PLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Panel Layout Considerations . . . . . . . . .
Contents 5 6 7 8 viii CPU Memory: Data Types and Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 Direct Addressing of the CPU Memory Areas . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 SIMATIC Indirect Addressing of the CPU Memory Areas . . . . . . . . . . . . . . 5-13 5.3 Memory Retention for the S7-200 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.4 Using Your Program to Store Data Permanently . . . . . . . . . . . . . . . . . . . .
Contents 9 10 SIMATIC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1 SIMATIC Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 SIMATIC Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3 SIMATIC Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.
Contents A S7-200 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 General Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.2 Specifications for the CPU 221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 A.3 Specifications for the CPU 222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 A.
Introducing the S7-200 Micro PLC 1 The S7-200 series is a line of micro-programmable logic controllers (Micro PLCs) that can control a variety of automation applications. Figure 1-1 shows an S7-200 Micro PLC. The compact design, expandability, low cost, and powerful instruction set of the S7-200 Micro PLC make a perfect solution for controlling small applications. In addition, the wide variety of CPU sizes and voltages provides you with the flexibility you need to solve your automation problems.
Introducing the S7-200 Micro PLC 1.1 Comparing the Features of the S7-200 Micro PLCs Equipment Requirements Figure 1-2 shows the basic S7-200 Micro PLC system, which includes an S7-200 CPU, a personal computer, STEP 7-Micro/WIN 32, version 3.0 programming software, and a communications cable. In order to use a personal computer (PC), you must have one of the following: A PC/PPI cable A communications processor (CP) and multipoint interface (MPI) cable A multipoint interface (MPI) card.
Introducing the S7-200 Micro PLC Table 1-1 Summary of the S7-200 CPUs CPU 221 Feature CPU 222 CPU 224 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Physical Size of Unit 90 mm x 80 mm x 62 mm 9
Introducing the S7-200 Micro PLC 1.2 Major Components of the S7-200 Micro PLC An S7-200 Micro PLC consists of an S7-200 CPU alone or with a variety of optional expansion modules. S7-200 CPU The S7-200 CPU combines a central processing unit (CPU), power supply, and discrete I/O points into a compact, stand-alone device. The CPU executes the program and stores the data for controlling the automation task or process.
Introducing the S7-200 Micro PLC Figure 1-3 shows the S7-200 CPU. Status LEDs Top terminal door Power terminal Output terminal Cartridge Front access door RUN STOP switch Potentiometer Expansion I/O connection Communication Port Bottom terminal door Input terminal Sensor power Figure 1-3 S7-200 CPU Expansion Modules The S7-200 CPU provides a certain number of local I/O. Adding an expansion module provides additional input or output points (see Figure 1-4).
Introducing the S7-200 Micro PLC 1-6 S7-200 Programmable Controller System Manual C79000-G7076-C233-01
2 Installing an S7-200 PLC The installation of the S7-200 equipment is designed to be easy. You can use the mounting holes to attach the modules to a panel, or you can use the built-in clips to mount the modules onto a standard (DIN) rail. The small size of the S7-200 allows you to make efficient use of space. This chapter provides guidelines for installing and wiring your S7-200 system. Chapter Overview Section Description Page 2.1 Panel Layout Considerations 2-2 2.
Installing an S7-200 PLC 2.1 Panel Layout Considerations Installation Configuration You can install an S7-200 either on a panel or on a standard rail. You can mount the S7-200 either horizontally or vertically. You can connect the S7-200 to expansion modules by one of these methods: A flexible ribbon cable with mating connector is built into the I/O module for easy connection to the PLC or another expansion module.
Installing an S7-200 PLC Clearance Requirements for Installing an S7-200 PLC Use the following guidelines as you plan your installation: The S7-200 CPU and expansion modules are designed for natural convection cooling. You must provide a clearance of at least 25 mm (1 in.), both above and below the units, for proper cooling. See Figure 2-2. Continuous operation of all electronic products at maximum ambient temperature and load reduces their life.
Installing an S7-200 PLC Standard Rail Requirements The S7-200 CPU and expansion modules can be installed on a standard (DIN) rail (DIN EN 50 022). Figure 2-3 shows the dimensions for this rail. 1.0 mm (0.04 in.) 35 mm (1.38 in.) 7.5 mm (0.30 in.) Figure 2-3 Standard Rail Dimensions Panel-Mounting Dimensions S7-200 CPUs and expansion modules include mounting holes to facilitate installation on panels.
Installing an S7-200 PLC 4 mm (0.16 in.) 120.5 mm (4.74 in.) 4 mm (0.16 in.) 112.5 mm (4.43 in.) 88 mm (3.46 in.) 96 mm (3.78 in.) CPU 224 80 mm (3.15 in.) ÁÁ 4 mm (0.16 in.) Figure 2-5 Mounting Dimensions for a CPU 224 Mounting holes (M4 or No. 8) Existing CPU or Expansion Module 4 mm (0.16 in.) ÁÁ ÁÁ Á Á 8-Point Expansion Module ÁÁ ÁÁ Á Á 4 mm (0.16 in.) 96 mm (3.78 in.) 16-Point Expansion Module 88 mm (3.46 in.) 80 mm (3.15 in.) ÁÁ ÁÁ 38 mm (1.50 in.) 9.5 mm* (0.37 in.) 63.
Installing an S7-200 PLC 2.2 Installing and Removing an S7-200 Micro PLC or Expansion Module Mounting an S7-200 Micro PLC or Expansion Module onto a Panel ! Warning Attempts to install or remove S7-200 CPUs or related equipment with power applied could cause electric shock or faulty operation of equipment. Failure to disable all power to the S7-200 and related equipment during installation or removal procedures may result in death or serious personal injury, and/or damage to equipment.
Installing an S7-200 PLC Installing an S7-200 Micro PLC or Expansion Module onto a Standard Rail ! Warning Attempts to install or remove S7-200 CPUs or related equipment when they are powered up could cause electric shock or faulty operation of equipment. Failure to disable all power to the S7-200 CPUs and related equipment during installation or removal procedures may result in death or serious personal injury, and/or damage to equipment.
Installing an S7-200 PLC Removing the S7-200 Micro PLC or Expansion Module ! Warning Attempts to install or remove S7-200 CPUs or related equipment when they are powered up could cause electric shock or faulty operation of equipment. Failure to disable all power to the S7-200 CPUs and related equipment during installation or removal procedures may result in death or serious personal injury, and/or damage to equipment.
Installing an S7-200 PLC 2.3 ! Installing the Field Wiring Warning Attempts to install or remove S7-200 CPUs or related equipment when they are powered up could cause electric shock or faulty operation of equipment. Failure to disable all power to the S7-200 CPUs and related equipment during installation or removal procedures may result in death or serious personal injury, and/or damage to equipment.
Installing an S7-200 PLC ! Warning Control devices can fail in an unsafe condition, resulting in unexpected operation of controlled equipment. Such unexpected action could result in death or serious personal injury, and/or equipment damage. Consider using an emergency stop function, electromechanical overrides, or other redundant safeguards that are independent of the programmable controller.
Installing an S7-200 PLC The following descriptions are an introduction to general isolation characteristics of the S7-200 family, but some features may be different on specific products. Consult your product specifications in Appendix A for information about which circuits include isolation boundaries and the ratings of the boundaries. Isolation boundaries rated less than 1,500 VAC are designed as functional isolation only, and should not be depended on as safety boundaries.
Installing an S7-200 PLC Using the Removable Terminal Block Connector The removable terminal block connector (Figure 2-9) allows field wiring connections to remain fixed when you remove and re-install the S7-200 CPU and I/O expansion modules. To remove the terminal block connector from the CPU or expansion module, follow these steps: 1. Raise the top terminal door of the CPU or expansion module. 2. Insert a screwdriver in the notch in the middle of the terminal block as shown in Figure 2-9. 3.
Installing an S7-200 PLC Guidelines for AC Installation The following items are general wiring guidelines for AC installations. Refer to Figure 2-10. [a] Provide a single disconnect switch that removes power from the CPU, all input circuits, and all output (load) circuits. [b] Provide overcurrent devices to protect the CPU power supply, the output points, and the input points. You can also fuse each output point individually for greater protection.
Installing an S7-200 PLC Guidelines for DC Installation The following items are general wiring guidelines for DC installations. Refer to Figure 2-11. [a] Provide a single disconnect switch that removes power from the CPU, all input circuits, and all output (load) circuits. [b] Provide overcurrent devices to protect the CPU power supply, [c] the output points, and [d] the input points. You can also fuse each output point individually for greater protection.
Installing an S7-200 PLC Floating [f] or Grounded [g] [a] L1 N PE AC [h] [g] DC [f] [e] [b] [c] DO DI PS S7-200 DC/DC/DC M DO EM 222 DC DI EM 221 DC [d] 24 VDC Figure 2-11 L+ M DC System Installation S7-200 Programmable Controller System Manual C79000-G7076-C233-01 2-15
Installing an S7-200 PLC 2.4 Using Suppression Circuits General Guidelines Equip inductive loads with suppression circuits that limit voltage rise on loss of power. Use the following guidelines to design adequate suppression. The effectiveness of a given design depends on the application, and you must verify it for a particular use. Be sure all components are rated for use in the application.
Installing an S7-200 PLC Protecting Relays That Control DC Power Resistor/capacitor networks, as shown in Figure 2-14, can be used for low voltage (30 V) DC relay applications. Connect the network across the load. R+ R C where minimum R = 12 Ω +VDC Inductor Figure 2-14 V DC IL IL C + I LK where K is 0.5 µF/A to 1 µF/A Resistor/Capacitor Network on Relay-Driven DC Load You can also use diode suppression, as shown in Figure 2-12 and Figure 2-13, for DC relay applications.
Installing an S7-200 PLC 2.5 Power Considerations The S7-200 base units have an internal power supply that provides power for the base unit, the expansion modules, and other 24 VDC user power requirements. Use the following information as a guide for determining how much power (or current) the base unit can provide for your configuration.
Installing an S7-200 PLC Calculating a Sample Power Requirement Table 2-1 shows a sample calculation of the power requirements for an S7-200 Micro PLC that includes the following: CPU 224 AC/DC/Relay 3 each EM 223 8 DC In/8 Relay Out 1 each EM 221 8 DC In This installation has a total of 46 inputs and 34 outputs.
Installing an S7-200 PLC Calculating Your Power Requirement Use the table below to determine how much power (or current) the CPU can provide for your configuration. Refer to Appendix A for the power budgets of your CPU and the power requirements of your expansion modules.
Getting Started with an S7-200 Programming System 3 This chapter describes how to set up an S7-200 programming system. The S7-200 programming system described in this chapter consists of: S An S7-200 CPU S A PC or programming device with STEP 7-Micro/WIN 32 installed S An interconnecting cable Chapter Overview Section Description Page 3.1 Overview 3-2 3.2 Quick Start for STEP 7-Micro/WIN 32 3-3 3.3 How Do I Set Up Communications Using the PC/PPI Cable? 3-5 3.
Getting Started with an S7-200 Programming System 3.1 Overview General Information You will need to base your installation on the following criteria: S The operating system that you are using (Windows 95, Windows 98, or Windows NT 4.
Getting Started with an S7-200 Programming System 3.2 Quick Start for STEP 7-Micro/WIN 32 Pre-Installation Instructions Before running the setup procedure, do the following: S If a previous version of STEP 7-Micro/WIN 32 is installed, back up all STEP 7-Micro/WIN projects to diskette. S Make sure all applications are closed, including the Microsoft Office toolbar. S Be sure the cable between your personal computer and the CPU is connected. See Section 3.3 for instructions.
Getting Started with an S7-200 Programming System " Project Edit View PLC Debug Tools Windows Help View Program Block Symbol Table Status Chart Data Block System Block Cross Reference Communications Figure 3-1 View Menu of STEP 7-Micro/WIN 32 Common Problem List for Single Connection User The following situations can cause the communication to fail: 3-4 S Wrong baud rate: Correct the baud rate S Wrong station address: Correct the station address S PC/PPI cable set incorrectly: Check DIP s
Getting Started with an S7-200 Programming System 3.3 How Do I Set Up Communications Using the PC/PPI Cable? This section explains how to set up communications between an S7-200 CPU and your personal computer using the PC/PPI cable. This is single master configuration with no other hardware (such as a modem or a programming device) installed. How Do I Connect My Computer to the CPU? Figure 3-2 shows a typical configuration for connecting your personal computer to your CPU with the PC/PPI cable.
Getting Started with an S7-200 Programming System How Do I Verify the Default Parameters for My Interface? You can verify the default parameters for your interface by following the steps below: 1. In the STEP 7-Micro/WIN 32 window, click the Communications icon, or select View > Communications from the menu. The Communications Setup dialog box appears. 2. In the Communications Setup dialog box, double-click on the icon for the PC/PPI cable. The Setting the PG/PC Interface dialog box appears.
Getting Started with an S7-200 Programming System Communications Links Communications Setup PC/PPI cable Address: 0 " DoubleSetting click the icon representing the PLC the PG/PC Interface you wish to communicate with. Access Path Double click the Point module icon to change to Access of Application: communication parameters.
Getting Started with an S7-200 Programming System " Setting the PG/PC Interface Access Path Properties - PC/PPI cable (PPI) Local Connection PPI Station Parameters Address: 0 Timeout: 1s Network Parameters Multiple Master Network Transmission Rate: 9.
Getting Started with an S7-200 Programming System 3.4 How Do I Go Online With the S7-200 CPU? Once you have installed STEP 7-Micro/WIN 32 software on your PC and set up communications with the PC/PPI cable, you are ready to go online with the S7-200 CPU. (If you are using a programming device, the STEP 7-Micro/WIN 32 is already installed.) Follow the steps below to go online with the S7-200 CPU: 1.
Getting Started with an S7-200 Programming System 3.5 How Do I Change the Communications Parameters for My PLC? Once you are online with the S7-200 CPU, you can verify or change the communications parameters for your PLC. To change the communications parameters follow the steps below: 1. Click the System Block icon on the navigation bar, or select View > System Block from the menu. 2. The System Block dialog box appears. Click on the Port(s) tab (see Figure 3-6).
Basic Concepts for Programming an S7-200 CPU 4 Before you start to program your application using the S7-200 CPU, you should become familiar with some of the basic operational features of the CPU. Chapter Overview Section Description Page 4.1 Guidelines for Designing a Micro PLC System 4-2 4.2 Concepts of an S7-200 Program 4-5 4.3 Concepts of the S7-200 Programming Languages and Editors 4-6 4.4 Understanding the Differences between SIMATIC and IEC 1131-3 Instructions 4-10 4.
Basic Concepts for Programming an S7-200 CPU 4.1 Guidelines for Designing a Micro PLC System There are many methods for designing a Micro PLC system. This section provides some general guidelines that can apply to many design projects. Of course, you must follow the directives of your own company’s procedures and of the accepted practices of your own training and location. Figure 4-1 shows some of the basic steps in the design process. Partition your process or machine.
Basic Concepts for Programming an S7-200 CPU Creating the Functional Specifications Write the descriptions of operation for each section of the process or machine. Include the following topics: Input/output (I/O) points Functional description of the operation Permissive states (states that must be achieved before allowing action) for each actuator (solenoids, motors, drives, etc.
Basic Concepts for Programming an S7-200 CPU Specifying the Operator Stations Based on the requirements of the functional specifications, create drawings of the operator stations. Include the following items: Overview showing the location of each operator station in relation to the process or machine Mechanical layout of the devices (display, switches, lights, etc.
Basic Concepts for Programming an S7-200 CPU 4.2 Concepts of an S7-200 Program Relating the Program to Inputs and Outputs The basic operation of the S7-200 CPU is very simple: The CPU reads the status of the inputs. The program that is stored in the CPU uses these inputs to evaluate the control logic. As the program runs, the CPU updates the data. The CPU writes the data to the outputs. Figure 4-2 shows a simple diagram of how an electrical relay diagram relates to the S7-200 CPU.
Basic Concepts for Programming an S7-200 CPU 4.3 Concepts of the S7-200 Programming Languages and Editors The S7-200 CPUs offer many types of instructions that allow you to solve a wide variety of automation tasks. There are two basic instruction sets available in the S7-200 CPU: SIMATIC and IEC 1131-3. Also, our PC-based programming software, STEP 7-Micro/WIN 32, provides different editor choices that allow you to create control programs with these instructions.
Basic Concepts for Programming an S7-200 CPU As you can see from Figure 4-3, this text-based concept is very similar to assembly language programming. The CPU executes each instruction in the order dictated by the program, from top to bottom, and then restarts at the top. STL and assembly language are also similar in another sense. S7-200 CPUs use a logic stack to resolve the control logic (see Figure 4-4).
Basic Concepts for Programming an S7-200 CPU Ladder Logic Editor The STEP 7-Micro/WIN 32 Ladder Logic (LAD) editor allows you to build programs that resemble the equivalent of an electrical wiring diagram. Ladder programming is probably the method of choice for many PLC programmers and maintenance personnel. Basically, the ladder programs allow the CPU to emulate the flow of electric current from a power source, through a series of logical input conditions that in turn enable logical output conditions.
Basic Concepts for Programming an S7-200 CPU Function Block Diagram Editor The STEP 7-Micro/WIN 32 Function Block Diagram (FBD) editor allows you to view the instructions as logic boxes that resemble common logic gate diagrams. There are no contacts and coils as found in the LAD editor, but there are equivalent instructions that appear as box instructions. The program logic is derived from the connections between these box instructions.
Basic Concepts for Programming an S7-200 CPU 4.4 Understanding the Differences between SIMATIC and IEC 1131-3 Instructions SIMATIC Instruction Set Most PLCs offer similar basic instructions, but there are usually small differences in their appearance, operation, etc. from vendor to vendor. The SIMATIC instruction set is designed for the S7-200 PLCs. These instructions may look and operate slightly differently when compared to similar instructions in another brand of PLC.
Basic Concepts for Programming an S7-200 CPU The main points to consider when you select IEC 1131-3 instructions are: It is usually easier to learn how to create programs for different brands of PLCs. Fewer instructions are available (as specified by the standard) but you can always use many of the SIMATIC instructions as well. Some instructions operate differently than their SIMATIC counterparts (timers, counters, multiply, divide, etc.) These instructions may have longer execution times.
Basic Concepts for Programming an S7-200 CPU Table 4-3 IEC 1131-3 Complex Data Types Complex Data Types TON1 Description On-Delay Timer Address Range 1 ms T32, T96 10 ms T33 to T36, T97 to T100 100 ms T37 to T63, T101 to T255 TOF Off-Delay Timer 1 ms T32, T96 10 ms T33 to T36, T97 to T100 100 ms T37 to T63, T101 to T255 TP Pulse Timer (See Note 1) 1 ms T32, T96 10 ms T33 to T36, T97 to T100 100 ms T37 to T63, T101 to T255 CTU Up Counter 0 to 255 CTD Down Counter 0 to 255 CTUD Up/
Basic Concepts for Programming an S7-200 CPU Strong data type checking is performed only within IEC 1131-3 modes. See Table 4-4.
Basic Concepts for Programming an S7-200 CPU No Data Type Checking The no data type checking mode is available only for SIMATIC global variables where the data types are not selectable. In this mode, all data types of equivalent size are automatically assigned to the symbol. For example, a symbol that is assigned the address VD100 is assigned the data types shown in Table 4-6 automatically by STEP 7-Micro/WIN 32.
Basic Concepts for Programming an S7-200 CPU Selecting Between SIMATIC and IEC 1131-3 Programming Modes Since IEC 1131-3 is strongly data typed, and SIMATIC is not strongly data typed, STEP 7-Micro/WIN 32 does not allow you to move programs between the two different editing modes. You must choose a preferred editing mode. Overloaded Instructions Overloaded instructions support a range of data types.
Basic Concepts for Programming an S7-200 CPU Data types for directly represented parameters are determined by examining other typed parameters included within the instruction. When an instruction parameter type is configured to use a variable that is of a specific type, all directly represented parameters will be assumed to be of that type. Table 4-8 and Table 4-9 show examples of data types for directly represented parameters.
Basic Concepts for Programming an S7-200 CPU Table 4-10 Conversion Instructions Conversion Instruction Strong Data Type Checking Allowed Operands Data Type Checking Allowed Operands BYTE to INT IN: OUT: BYTE INT IN: OUT: BYTE WORD, INT INT to BYTE IN: OUT: INT BYTE IN: OUT: WORD, INT BYTE INT to DINT IN: OUT DINT DINT IN: OUT: WORD, INT DWORD, DINT DINT to INT IN: OUT: DINT INT IN: OUT: DWORD, DINT WORD, INT DINT to REAL IN: OUT: DINT REAL IN: OUT: DWORD, DINT REAL REAL to DINT
Basic Concepts for Programming an S7-200 CPU 4.5 Basic Elements for Constructing a Program The S7-200 CPU continuously executes your program to control a task or process. You create this program with STEP 7-Micro/WIN 32 and download it to the CPU. From the main program, you can call different subroutines or interrupt routines. Organizing the Program Programs for an S7-200 CPU are constructed from three basic elements: the main program, subroutines (optional), and interrupt routines (optional).
Basic Concepts for Programming an S7-200 CPU SIMATIC LAD MAIN PROGRAM OB1 Network 1 SM0.1 SBR0 EN SUBROUTINE 0 Network 1 SM0.0 100 MOV_B EN ENO IN OUT ATCH EN ENO SMB34 0 10 ENI INT EVNT INTERRUPT ROUTINE 0 Network 1 SM0.0 MOV_W EN ENO AIW4 Figure 4-7 IN OUT VW100 SIMATIC LAD Program for Using a Subroutine and an Interrupt Routine Statement List Main Program OB1 Network 1 LD SM0.1 CALL 0 //When first scan cycle //bit comes on //Call subroutine 0. Subroutine 0 Network 1 LD SM0.
Basic Concepts for Programming an S7-200 CPU SIMATIC FBD MAIN PROGRAM OB1 Network 1 SM0.1 SBR0 EN SUBROUTINE 0 Network 1 MOV_B EN ENO SM0.0 100 IN OUT ATCH EN ENO SMB34 0 10 ENI INT EVENT INTERRUPT ROUTINE 0 Network 1 SM0.0 AIW4 Figure 4-9 MOV_W EN ENO IN OUT VW100 SIMATIC FBD Program for Using a Subroutine and an Interrupt Routine IEC LAD MAIN PROGRAM Network 1 %SM0.1 SBR0 EN SUBROUTINE 0 Network 1 %SM0.
Basic Concepts for Programming an S7-200 CPU IEC FBD MAIN PROGRAM OB1 Network 1 %SM0.1 SBR0 EN SUBROUTINE 0 Network 1 %SM0.0 MOVE EN ENO 100 IN OUT ATCH EN ENO %SMB34 0 10 ENI EN INT EVENT INTERRUPT ROUTINE 0 Network 1 %SM0.
Basic Concepts for Programming an S7-200 CPU 4.6 Understanding the Scan Cycle of the CPU The S7-200 CPU is designed to execute a series of tasks, including your program, repetitively. This cyclical execution of tasks is called the scan cycle.
Basic Concepts for Programming an S7-200 CPU The CPU does not update analog inputs as part of the normal scan cycle unless digital filtering of analog inputs is enabled. Digital filtering is provided as a user selectable option and can be individually enabled for each analog input point. Digital filtering is intended for use with low-cost analog modules that do not provide filtering internal to the module. Digital filtering should be used in applications where the input signal varies slowly with time.
Basic Concepts for Programming an S7-200 CPU The CPU reserves the process-image output register in increments of eight bits (one byte). If the CPU or expansion module does not provide a physical output point for each bit of the reserved byte, you cannot reallocate these bits to subsequent modules in the I/O chain. When the CPU operating mode is changed from RUN to STOP, the digital outputs are set to the values defined in the Output Table, or are left in their current state (see Section 6.4).
Basic Concepts for Programming an S7-200 CPU 4.7 Selecting the Mode of Operation for the CPU The S7-200 CPU has two modes of operation: STOP: The CPU is not executing the program. You can download a program or configure the CPU when the CPU is in STOP mode. RUN: The CPU is running the program. The status LED on the front of the CPU indicates the current mode of operation.
Basic Concepts for Programming an S7-200 CPU Changing the Operating Mode with STEP 7-Micro/WIN 32 As shown in Figure 4-13, you can use STEP 7-Micro/WIN 32 to change the operating mode of the CPU. To enable the software to change the operating mode, you must set the mode switch on the CPU to either TERM or RUN.
Basic Concepts for Programming an S7-200 CPU 4.8 Creating a Password for the CPU All models of the S7-200 CPU provide password protection for restricting access to specific CPU functions. A password authorizes access to the CPU functions and memory: without a password, the CPU provides unrestricted access. When password protected, the CPU prohibits all restricted operations according to the configuration provided when the password was installed.
Basic Concepts for Programming an S7-200 CPU Configuring the CPU Password You can use STEP 7-Micro/WIN 32 to create the password for the CPU. Select the menu command View > System Block and click the Password tab. See Figure 4-14. Enter the appropriate level of access for the CPU, then enter and verify the password for the CPU.
Basic Concepts for Programming an S7-200 CPU What to Do If You Forget the CPU Password If you forget the CPU password, you must clear the CPU memory and reload your program. Clearing the CPU memory puts the CPU in STOP mode and resets the CPU to the factory-set defaults, except for the CPU address, baud rate, and the time-of-day clock. To clear your program in the CPU, select the PLC > Clear... menu command to display the Clear dialog box.
Basic Concepts for Programming an S7-200 CPU 4.9 Debugging and Monitoring Your Program STEP 7-Micro/WIN 32 provides a variety of tools for debugging and monitoring your program. Using Single/Multiple Scans to Monitor Your Program You can specify that the CPU execute your program for a limited number of scans (from 1 scan to 65,535 scans). By selecting the number of scans for the CPU to run, you can monitor the program as it changes the process variables.
Basic Concepts for Programming an S7-200 CPU Using a Status Chart to Monitor and Modify Your Program As shown in Figure 4-16, you can use a Status Chart to read, write, force, and monitor variables while the program is running. Use the menu command View > Status Chart. S The status chart toolbar icons are shown in the STEP 7-Micro/WIN 32 toolbar area.
Basic Concepts for Programming an S7-200 CPU Displaying the Status of the Program in Ladder Logic You can monitor the status of the ladder program by using STEP 7-Micro/WIN 32. STEP 7-Micro/WIN 32 must be displaying ladder logic. Ladder status displays the status of all instruction operand values. See Figure 4-17. All status is based upon the value of these elements that are read at the end of a PLC scan cycle.
Basic Concepts for Programming an S7-200 CPU Displaying the Status of the Program in Function Block Diagram You can monitor the status of the FBD program by using STEP 7-Micro/WIN 32. STEP 7-Micro/WIN 32 must be displaying FBD. FBD status displays the status of all instruction operand values. All status is based upon the values of operands that were read at the end of a PLC scan cycle.
Basic Concepts for Programming an S7-200 CPU Forcing Specific Values The S7-200 CPU allows you to force any or all of the I/O points (I and Q bits). In addition, you can also force up to 16 internal memory values (V or M) or analog I/O values (AI or AQ). V memory or M memory values can be forced in bytes, words, or double words. Analog values are forced as words only, on even-numbered byte boundaries (such as AIW6 or AQW14). All forced values are stored in the permanent EEPROM memory of the CPU.
Basic Concepts for Programming an S7-200 CPU Reads the forced values from the CPU. Unforces the current selection. Tools Windows Help Unforces all CPU forced values. Forces the current selection. Status Chart Address 1 “Start_1” 2 “Start_2” 3 “Stop_1” 4 “Stop_2” 5 6 VB100 7 VW100 8 VD100 9 VD100.
Basic Concepts for Programming an S7-200 CPU 4.10 Error Handling for the S7-200 CPU The S7-200 CPU classifies errors as either fatal errors or non-fatal errors. You can use STEP 7-Micro/WIN 32 to view the error codes that were generated by the error. Select PLC > Information from the menu bar to view these errors. Figure 4-21 shows the dialog box that displays the error code and the description of the error. Refer to Appendix B for a complete listing of the error codes.
Basic Concepts for Programming an S7-200 CPU Responding to Fatal Errors Fatal errors cause the CPU to stop the execution of your program. Depending upon the severity of the fatal error, it can render the CPU incapable of performing any or all functions. The objective for handling fatal errors is to bring the CPU to a safe state from which the CPU can respond to interrogations about the existing error conditions.
Basic Concepts for Programming an S7-200 CPU Responding to Non-Fatal Errors Non-fatal errors can degrade some aspect of the CPU performance, but they do not render the CPU incapable of executing your program or updating the I/O. As shown in Figure 4-21, you can use STEP 7-Micro/WIN 32 to view the error codes that were generated by the non-fatal error. There are three basic categories of non-fatal errors: S Run-time errors.
CPU Memory: Data Types and Addressing Modes 5 The S7-200 CPU provides specialized areas of memory to make the processing of the control data faster and more efficient. Chapter Overview Section Description Page 5.1 Direct Addressing of the CPU Memory Areas 5-2 5.2 SIMATIC Indirect Addressing of the CPU Memory Areas 5-13 5.3 Memory Retention for the S7-200 CPU 5-15 5.4 Using Your Program to Store Data Permanently 5-20 5.
CPU Memory: Data Types and Addressing Modes 5.1 Direct Addressing of the CPU Memory Areas The S7-200 CPU stores information in different memory locations that have unique addresses. You can explicitly identify the memory address that you want to access. This allows your program to have direct access to the information. Using the Memory Address to Access Data To access a bit in a memory area, you specify the address, which includes the memory area identifier, the byte address, and the bit number.
CPU Memory: Data Types and Addressing Modes You can access data in many CPU memory areas (V, I, Q, M, S, L, and SM) as bytes, words, or double words by using the byte-address format. To access a byte, word, or double word of data in the CPU memory, you must specify the address in a way similar to specifying the address for a bit. This includes an area identifier, data size designation, and the starting byte address of the byte, word, or double-word value, as shown in Figure 5-2.
CPU Memory: Data Types and Addressing Modes Representation of Numbers Table 5-1 shows the range of integer values that can be represented by the different sizes of data. Real (or floating-point) numbers are represented as 32-bit, single-precision numbers whose format is: +1.175495E-38 to +3.402823E+38 (positive), and -1.175495E-38 to -3.402823E+38 (negative). Real number values are accessed in double-word lengths.
CPU Memory: Data Types and Addressing Modes Addressing the Variable (V) Memory Area You can use V memory to store intermediate results of operations being performed by the control logic in your program. You can also use V memory to store other data pertaining to your process or task. You can access the V memory area in bits, bytes, words, or double words. Format: Bit Byte, Word, Double Word V[byte address].[bit address] V10.
CPU Memory: Data Types and Addressing Modes Addressing the Local (L) Memory Area The S7-200 PLCs provide 64 bytes of local (L) memory of which 60 can be used as scratchpad memory or for passing formal parameters to subroutines. If you are programming in either LAD or FBD, STEP 7-Micro/WIN 32 reserves the last four bytes of local memory for its own use. If you program in STL, all 64 bytes of L memory are accessible, but it is recommended that you do not use the last four bytes of L memory.
CPU Memory: Data Types and Addressing Modes Addressing the Timer (T) Memory Area In the S7-200 CPU, timers are devices that count increments of time. The S7-200 timers have resolutions (time-base increments) of 1 ms, 10 ms, or 100 ms. There are two variables that are associated with a timer: Current value: this 16-bit signed integer stores the amount of time counted by the timer. Timer bit: this bit is set or cleared as a result of comparing the current and the preset value.
CPU Memory: Data Types and Addressing Modes Addressing the Counter (C) Memory Area In the S7-200 CPU, counters are devices that count each low-to-high transition event on the counter input(s). The CPU provides three types of counters: one type counts up only, one type counts down, and one type counts both up and down. There are two variables that are associated with a counter: Current value: this 16-bit signed integer stores the accumulated count.
CPU Memory: Data Types and Addressing Modes Addressing the Analog Inputs (AI) The S7-200 converts a real-world, analog value (such as temperature or voltage) into a word-length (16-bit) digital value. You access these values by the area identifier (AI), size of the data (W), and the starting byte address. Since analog inputs are words and always start on even-number bytes (such as 0, 2, or 4), you access them with even-number byte addresses (such as AIW0, AIW2, or AIW4), as shown in Figure 5-5.
CPU Memory: Data Types and Addressing Modes Addressing the Accumulators (AC) Accumulators are read/write devices that can be used like memory. For example, you can use accumulators to pass parameters to and from subroutines and to store intermediate values used in a calculation. The CPU provides four 32-bit accumulators (AC0, AC1, AC2, and AC3). You can access the data in the accumulators as bytes, words, or double words.
CPU Memory: Data Types and Addressing Modes Addressing the High-Speed Counters (HC) High-speed counters are designed to count very high-speed events independent of the CPU scan. High-speed counters have a signed, 32-bit integer counting value (or current value). To access the count value for the high-speed counter, you specify the address of the high-speed counter, using the memory type (HC) and the counter number (such as HC0).
CPU Memory: Data Types and Addressing Modes Using Constant Values You can use a constant value in many of the S7-200 instructions. Constants can be bytes, words, or double words. The CPU stores all constants as binary numbers, which can then be represented in decimal, hexadecimal, ASCII or floating point formats. Decimal Format: Hexadecimal Format: ASCII Format: Real or Floating-Point Format: [decimal value] 16#[hexadecimal value] .
CPU Memory: Data Types and Addressing Modes 5.2 SIMATIC Indirect Addressing of the CPU Memory Areas Indirect addressing uses a pointer to access the data in memory. The S7-200 CPU allows you to use pointers to address the following memory areas indirectly: I, Q, V, M, S, T (current value only), and C (current value only). You cannot address individual bit or analog values indirectly. Creating a Pointer To address a location in memory indirectly, you must first create a pointer to that location.
CPU Memory: Data Types and Addressing Modes Modifying Pointers You can change the value of a pointer. Since pointers are 32-bit values, use double-word instructions to modify pointer values. Simple mathematical operations, such as adding or incrementing, can be used to modify pointer values. Remember to adjust for the size of the data that you are accessing: When accessing bytes, increment the pointer value by one.
CPU Memory: Data Types and Addressing Modes 5.3 Memory Retention for the S7-200 CPU The S7-200 CPU provides several methods to ensure that your program, the program data, and the configuration data for your CPU are properly retained. See Figure 5-11. The CPU provides an EEPROM to store permanently all of your program, user-selected data areas, and the configuration data for your CPU. The CPU provides a super capacitor that maintains the integrity of the RAM after power has been removed from the CPU.
CPU Memory: Data Types and Addressing Modes User program CPU configuration Data block (DB1): up to the maximum V memory range S7-200 CPU User program User program CPU configuration CPU configuration User program CPU configuration DB1 V memory V memory (permanent area) M memory M memory (permanent area) Timer and counter current values Figure 5-12 RAM EEPROM Downloading the Elements of the Project When you upload a project from the CPU, as shown in Figure 5-13, the CPU configuration is upload
CPU Memory: Data Types and Addressing Modes Automatically Saving the Data from the Bit Memory (M) Area When the CPU Loses Power If the first 14 bytes of M memory (MB0 to MB13) are configured to be retentive, they are permanently saved to the EEPROM when the CPU loses power. As shown in Figure 5-14, the CPU moves these retentive areas of M memory to the EEPROM. In STEP 7-Micro/WIN 32, the default setting is set to off.
CPU Memory: Data Types and Addressing Modes At power on, the CPU checks the RAM to verify that the super capacitor successfully maintained the data stored in RAM memory. If the RAM was successfully maintained, the retentive areas of RAM are left unchanged. As shown in Figure 5-16, the non-retentive areas of V memory are restored from the corresponding permanent area of V memory in the EEPROM.
CPU Memory: Data Types and Addressing Modes Defining Retentive Ranges of Memory You can define up to six retentive ranges to select the areas of memory you want to retain through power cycles (see Figure 5-18). You can define ranges of addresses in the following memory areas to be retentive: V, M, C, and T. For timers, only the retentive timers (TONR) can be retained. In STEP 7-Micro/WIN 32 the default is that M memory is defined as non-retentive.
CPU Memory: Data Types and Addressing Modes 5.4 Using Your Program to Store Data Permanently You can save a value (byte, word, or double word) stored in V memory to EEPROM. This feature can be used to store a value in any location of the permanent V memory area. A save-to-EEPROM operation typically affects the scan time by up to 5 ms. The value written by the save operation overwrites any previous value stored in the permanent V memory area of the EEPROM.
CPU Memory: Data Types and Addressing Modes Limiting the Number of Programmed Saves to EEPROM Since the number of save operations to the EEPROM is limited (100,000 minimum, and 1,000,000 typical), you should ensure that only necessary values are saved. Otherwise, the EEPROM can be worn out and the CPU can fail. Typically, you perform save operations at the occurrence of specific events that occur rather infrequently.
CPU Memory: Data Types and Addressing Modes 5.5 Using a Memory Cartridge to Store Your Program The CPUs support an optional memory cartridge that provides a portable EEPROM storage for your program. The CPU stores the following elements on the memory cartridge: User program Data stored in the permanent V memory area of the EEPROM CPU configuration For more information about the memory cartridge, see Appendix A.
CPU Memory: Data Types and Addressing Modes You can install or remove the memory cartridge while the CPU is powered on. To install the memory cartridge, remove the plastic cover from the PLC, and insert the memory cartridge on the PLC. (The memory cartridge is keyed for proper installation.) After the memory cartridge is installed, use the following procedure to copy the program. 1. If the program has not already been downloaded to the CPU, download the program. 2.
CPU Memory: Data Types and Addressing Modes Restoring the Program and Memory with a Memory Cartridge To transfer the program from a memory cartridge to the CPU, you must cycle the power to the CPU with the memory cartridge installed. As shown in Figure 5-21, the CPU performs the following tasks after a power cycle (when a memory cartridge is installed): The RAM is cleared. The contents of the memory cartridge are copied to the RAM.
CPU and Input/Output Configuration 6 The inputs and outputs are the system control points: the inputs monitor the signals from the field devices (such as sensors and switches), and the outputs control pumps, motors, or other devices in your process. You can have local I/O (provided by the CPU) or expansion I/O (provided by an expansion I/O module). The S7-200 CPUs also provide high-speed I/O. Chapter Overview Section Description Page 6.1 Local I/O and Expansion I/O 6-2 6.
CPU and Input/Output Configuration 6.1 Local I/O and Expansion I/O The inputs and outputs are the system control points: the inputs monitor the signals from the field devices (such as sensors and switches), and the outputs control pumps, motors, or other devices in your process. You can have local I/O (provided by the CPU) or expansion I/O (provided by an expansion I/O module): The S7-200 CPU provides a certain number of digital local I/O points.
CPU and Input/Output Configuration Examples of Local and Expansion I/O Figure 6-1 and Figure 6-2 provide examples that show how different hardware configurations affect the I/O numbering. Notice that some of the configurations contain gaps in the addressing that cannot be used by your program. CPU 221 Process-image I/O register assigned to physical I/O: I0.0 I0.1 I0.2 I0.3 I0.4 I0.5 Figure 6-1 Q0.0 Q0.1 Q0.2 Q0.
CPU and Input/Output Configuration 6.2 Using the Selectable Input Filter to Provide Noise Rejection The S7-200 CPUs allow you to select an input filter that defines a delay time (selectable from 0.2 ms to 12.8 ms) for some or all of the local digital input points. (See Appendix A for information about your particular CPU.) As shown in Figure 6-3, each delay specification applies to groups of four input points.
CPU and Input/Output Configuration 6.3 Pulse Catch The S7-200 CPUs provide a pulse catch feature for each of the local digital inputs. The pulse catch feature allows you to capture high-going pulses or low-going pulses that are of such a short duration that they would not always be seen when the CPU reads the digital inputs at the beginning of the scan cycle. Pulse catch operation can be individually enabled on each of the local digital inputs.
CPU and Input/Output Configuration A block diagram of the digital input circuit is shown in Figure 6-5. External digital input Optical isolation Pulse catch function Digital input filter Input to CPU Pulse catch enable Figure 6-5 Digital Input Circuit The response of an enabled pulse catch circuit to various input conditions is shown in Figure 6-6.
CPU and Input/Output Configuration To access the pulse catch configuration screen, select the menu command View > System Block from the main menu bar and click on the Pulse Catch Bits tab. Figure 6-7 shows the Pulse Catch configuration screen. The default CPU configuration and the default STEP 7-Micro/WIN 32 configuration are disabled for all inputs.
CPU and Input/Output Configuration 6.4 Using the Output Table to Configure the States of the Outputs The S7-200 CPU provides the capability either to set the state of the digital output points to known values upon a transition to the STOP mode, or to leave the outputs in the state they were in before the transition to the STOP mode. The output table is part of the CPU configuration data that is downloaded and stored in the CPU memory. The configuration of output values applies only to the digital outputs.
CPU and Input/Output Configuration 6.5 Analog Input Filter With the CPU 222 and CPU 224, you can select software filtering on individual analog inputs. The filtered value is the average value of the sum of a preselected number of samples of the analog input. The filter specification (number of samples and dead band) is the same for all analog inputs for which filtering is enabled. The filter has a fast response feature to allow large changes to be quickly reflected in the filter value.
CPU and Input/Output Configuration 6.6 High-Speed I/O Your S7-200 CPU provides high-speed I/O for controlling high-speed events. For more information about the high-speed I/O provided by each CPU, refer to the specifications in Appendix A. High-Speed Counters The S7-200 CPUs provide integrated high-speed counter functions that count external events at rates up to 20 kHz without degrading the performance of the CPU.
CPU and Input/Output Configuration From this table you can see that if you are using HSC0 in modes 3 through 10 (Clock and Direction or any of the two-phase clocking modes), you cannot use HSC3 because HSC0 and HSC3 both use I0.1. The same is true for HSC4 and HSC5, which both use I0.4. You can use I0.0 through I0.3 for high-speed counter inputs, or you can configure these inputs to provide edge interrupt events.
CPU and Input/Output Configuration High-Speed Pulse Output The S7-200 CPUs support high-speed pulse outputs. Q0.0 and Q0.1 can either generate high-speed pulse train outputs (PTO) or perform pulse width modulation (PWM) control. The pulse train function provides a square wave (50% duty cycle) output for a specified number of pulses and a specified cycle time. The number of pulses can be specified from 1 to 4,294,967,295 pulses.
CPU and Input/Output Configuration 6.7 Analog Adjustments The analog adjustment potentiometers are located under the front access cover of the module. You can adjust these potentiometers to increase or decrease values that are stored in bytes of Special Memory (SMB28 and SMB29). These read-only values can be used by the program for a variety of functions, such as updating the current value for a timer or a counter, entering or changing the preset values, or setting limits.
CPU and Input/Output Configuration 6-14 S7-200 Programmable Controller System Manual C79000-G7076-C233-01
Setting Up Communications Hardware and Network Communications 7 This chapter describes communications using STEP 7-Micro/WIN 32, version 3.0. Previous versions of the software may operate differently. It also tells you how to set up your communications hardware and how to set up an S7-200 communications network. Chapter Overview Section Description Page 7.1 What Are My Communication Choices? 7-2 7.2 Installing and Removing Communication Interfaces 7-7 7.
Setting Up Communications Hardware and Network Communications 7.1 What Are My Communication Choices? You can arrange the S7-200 CPUs in a variety of configurations to support network communications. You can install the STEP 7-Micro/WIN 32 software on a personal computer (PC) that has a Windows 95, Windows 98, or Windows NT operating system, or you can install it on a SIMATIC programming device (such as a PG 740).
Setting Up Communications Hardware and Network Communications Master devices TD 200 OP15 CPU 224 CP card MPI cable (RS-485) CPU 221 CPU 224 CPU 221 CPU 224 Slave devices Figure 7-2 Example of a CP Card with Master and Slave Devices How Do I Choose My Communication Configuration? Table 7-1 shows the possible hardware configurations and baud rates that STEP 7-Micro/WIN 32 supports.
Setting Up Communications Hardware and Network Communications Data Communications Using the CP or MPI Card Siemens offers several network interface cards that you can put into a personal computer or SIMATIC programming device. These cards allow the PC or SIMATIC programming device to act as a network master. These cards contain dedicated hardware to assist the PC or programming device in managing a multiple-master network, and can support different protocols at several baud rates. See Table 7-1.
Setting Up Communications Hardware and Network Communications How Do I Set Up Communications within STEP 7-Micro/WIN 32? Within STEP 7-Micro/WIN 32, there is a Setup Communications dialog box that you can use to configure your communications setup. You can use one of the following ways to find this dialog box: S Select the menu command View > Communications. S Click the Communications icon on the STEP 7-Micro/WIN 32 screen (see Figure 7-3).
Setting Up Communications Hardware and Network Communications In the Communications Setup dialog box, double-click the top icon on the right-hand side. The Setting the PG/PC Interface dialog box appears. See Figure 7-4. Communications Links Communications Setup PC/PPI cable Address: 0 " DoubleSetting click the icon representing the PLC the PG/PC Interface you wish to communicate with. Access Path Double click the Point module icon to change to Access of Application: communication parameters.
Setting Up Communications Hardware and Network Communications 7.2 Installing and Removing Communication Interfaces You can install or remove communications hardware by using the Install/Remove Interfaces dialog box shown in Figure 7-5. On the left side of this dialog box is a list of hardware types that you have not installed yet. On the right side is a list of currently installed hardware types. If you are using the Windows NT 4.
Setting Up Communications Hardware and Network Communications Special Hardware Installation Information for Windows NT Users Installing hardware modules under the Windows NT operating system is slightly different from installing hardware modules under Windows 95. Although the hardware modules are the same for either operating system, installation under Windows NT requires more knowledge of the hardware that you want to install.
Setting Up Communications Hardware and Network Communications 7.3 Selecting and Changing Parameters Selecting the Correct Interface Parameter Set and Setting It Up When you have reached the Setting the PG/PC Interface dialog box, be sure that “Micro/WIN” appears in the Access Point of Application list box (see Figure 7-4).
Setting Up Communications Hardware and Network Communications Setting Up the PC/PPI Cable (PPI) Parameters This section explains how to set up the PPI parameters for the Windows 95, Windows 98, or Windows NT 4.0 operating systems, and for the PC/PPI cable. From the Setting the PG/PC Interface dialog box, if you are using the PC/PPI cable and you click the “Properties...” button, the properties sheet appears for PC/PPI cable (PPI). See Figure 7-7.
Setting Up Communications Hardware and Network Communications Follow these steps to set up the PPI parameters: 1. In the PPI tab, in the Station Parameters area, select a number in the Address box. This number indicates where you want STEP 7-Micro/WIN 32 to reside on the programmable controller network. The default station address for the personal computer on which you are running STEP 7-Micro/WIN 32 is station address 0. The default station address for the first PLC on your network is station address 2.
Setting Up Communications Hardware and Network Communications 6. Click the Local Connection tab. See Figure 7-8. 7. In the Local Connection tab, select the COM port to which your PC/PPI cable is connected. If you are using a modem, select the COM port to which the modem is connected and select the Use Modem check box. 8. Click the “OK” button to exit the Setting the PG/PC Interface dialog.
Setting Up Communications Hardware and Network Communications Note If you are using the PPI parameter set, STEP 7-Micro/WIN 32 does not support two different applications running on the same MPI or CP card at the same time. Close the other application before connecting STEP 7-Micro/WIN 32 to the network through the MPI or CP card.
Setting Up Communications Hardware and Network Communications Setting Up the CP or MPI Card (PPI) Parameters This section explains how to set up the PPI parameters for the Windows 95, Windows 98 or Windows NT 4.0 operating systems and the following hardware: CP 5511 CP 5611 MPI From the Setting the PG/PC Interface dialog box, if you are using any of the MPI or CP cards listed above along with the PPI protocol, and you click the “Properties...
Setting Up Communications Hardware and Network Communications Properties - MPI-ISA Card (PPI) PPI Station Parameters Address: 0 Timeout: 1s Network Parameters 4 Multiple Master Network Transmission Rate: 9.
Setting Up Communications Hardware and Network Communications 7.4 Communicating With Modems Setting Up the Communications Parameters When Using Modems To set up communications parameters between your programming device or PC and the CPU when using modems, you must use the module parameter set for the PC/PPI cable. Otherwise, the Configure Modems function is not available.
Setting Up Communications Hardware and Network Communications Communications Links Communications Setup Double click the icon representing the PLC you wish to communicate with. Double click the interface icon to change to communication parameters. Double click the modem icon to setup the modem parameters or dial to start modem communications.
Setting Up Communications Hardware and Network Communications 8. In the Communications Setup dialog box, double-click on the first modem icon. The Modem Setup dialog box for the local modem appears (Figure 7-12). 9. In the Local Modem area, select your modem type. If your modem is not listed, select the Add button to configure your modem. To do this, you must know the AT commands for your modem. Refer to the documentation for your modem. 10.
Setting Up Communications Hardware and Network Communications 11. The Configure dialog box appears (Figure 7-13). If you are using a predefined modem, the only field that you can edit in this dialog box is the Timeout area. The timeout is the length of time that the local modem attempts to set up a connection to the remote modem. If the time indicated in seconds in the Timeout field elapses before the connection is set up, the attempt to connect fails.
Setting Up Communications Hardware and Network Communications Setting Up The Remote Modem: 1. In the Communications Setup dialog box, double-click on the second modem icon (Figure 7-11). The Modem Setup dialog box for the remote modem appears (Figure 7-14). 2. In the Remote Modem area, select your modem type. If your modem is not listed, select the “Add” button to configure your modem. To do this, you must know the AT commands for your modem. Refer to the documentation for your modem. 3.
Setting Up Communications Hardware and Network Communications Configure Bausch Induline IL 14K4 (11-bit) Initialization String AT&F08K0X3&D0 Communication String *W=9600,8,E,1 Suffix &Y0&W0^M Program/Test Status Advanced...
Setting Up Communications Hardware and Network Communications 7. Disconnect your remote modem from your local machine (your programming device or PC). 8. Connect the remote modem to your S7-200 programmable controller. 9. Connect your local modem to your programming device or PC. Connecting the Modems: 1. To connect your modem, double-click on the Connect Modem icon in the Communications Setup dialog box. The Dial dialog box appears. See Figure 7-16. 2.
Setting Up Communications Hardware and Network Communications Using a 10-Bit Modem to Connect an S7-200 CPU to a STEP 7-Micro/WIN 32 Master Using STEP 7-Micro/WIN 32 on a PC with a Windows 95, Windows 98, or Windows NT operating system, or using a SIMATIC programming device (such as a PG 740) as a single-master device, you can connect to only one S7-200 CPU. You can use a Hayes-compatible 10-bit modem to communicate to a single remote S7-200 CPU.
Setting Up Communications Hardware and Network Communications This configuration allows only one master device and one slave device. In this configuration, the S7-200 controller requires one start bit, eight data bits, no parity bit, one stop bit, asynchronous communication, and a transmission speed of 9600 baud. The modem requires the settings listed in Table 7-2. Figure 7-18 shows the pin assignments for a 25-Pin to 9-Pin Adapter.
Setting Up Communications Hardware and Network Communications Using an 11-Bit Modem to Connect an S7-200 CPU to a STEP 7-Micro/WIN 32 Master Using STEP 7-Micro/WIN 32 on a PC with a Windows 95, Windows 98, or Windows NT operating system, or on a SIMATIC programming device (such as a PG 740) as a single-master device, you can connect to one or more S7-200 CPUs. Most modems are not capable of supporting the 11-bit protocol.
Setting Up Communications Hardware and Network Communications This configuration allows only one master device and supports only the PPI protocol. In order to communicate through the PPI interface, the S7-200 PLC requires that the modem use an 11-bit data string. In this mode, the S7-200 controller requires one start bit, eight data bits, one parity bit (even parity), one stop bit, asynchronous communication, and a transmission speed of 9600 baud. Many modems are not capable of supporting this data format.
Setting Up Communications Hardware and Network Communications 7.5 Network Overview Network Masters Figure 7-21 shows a configuration with a personal computer connected to several S7-200 CPUs. STEP 7-Micro/WIN 32 is designed to communicate with one S7-200 CPU at a time; however, you can access any CPU on the network. The CPUs in Figure 7-21 could be either slave or master devices. The TD 200 is a master device.
Setting Up Communications Hardware and Network Communications Network Communication Protocols The S7-200 CPUs support a variety of communication capabilities. Depending on the S7-200 CPU that you use, your network can support one or more of the following communication protocols: Point-to-Point Interface (PPI) Multipoint Interface (MPI) PROFIBUS These protocols are based upon the Open System Interconnection (OSI) seven-layer model of communications architecture.
Setting Up Communications Hardware and Network Communications PPI Protocol PPI is a master/slave protocol. In this protocol the master devices (other CPUs, SIMATIC programming devices, or TD 200s) send requests to the slave devices and the slave devices respond. Slave devices do not initiate messages, but wait until a master sends them a request or polls them for a response. All S7-200 CPUs act as slave devices on the network.
Setting Up Communications Hardware and Network Communications PROFIBUS Protocol The PROFIBUS protocol is designed for high-speed communications with distributed I/O devices (remote I/O). There are many PROFIBUS devices available from a variety of manufacturers. These devices range from simple input or output modules to motor controllers and programmable controllers. PROFIBUS networks usually have one master and several slave I/O devices.
Setting Up Communications Hardware and Network Communications 7.6 Network Components The communication port on each S7-200 enables you to connect it to a network bus. The information below describes this port, the connectors for the network bus, the network cable, and repeaters used to extend the network.
Setting Up Communications Hardware and Network Communications Network Connectors Siemens offers two types of networking connectors that you can use to connect multiple devices to a network easily. Both connectors have two sets of terminal screws to allow you to attach the incoming and outgoing network cables. Both connectors also have switches to bias and terminate the network selectively. One connector type provides only a connection to the CPU. The other adds a programming port (see Figure 7-23).
Setting Up Communications Hardware and Network Communications Switch position = On Terminated and biased Switch position = Off No termination or bias On Network connector with programming port Off Ä Ä TxD/RxD + TxD/RxD - A 220 Ω 390 Ω Cable shield Bare shielding (~12 mm or 1/2 in.) must contact the metal guides of all locations.
Setting Up Communications Hardware and Network Communications Network Repeaters Siemens provides network repeaters to connect PROFIBUS network segments. See Figure 7-24. The use of repeaters extends the overall network length, allows you to add devices to a network, and/or provides a way to isolate different network segments. PROFIBUS allows a maximum of 32 devices on a network segment of up to 1,200 m (3,936 ft.) at 9600 baud.
Setting Up Communications Hardware and Network Communications 7.7 Using the PC/PPI Cable with Other Devices and Freeport You can use the PC/PPI cable and the Freeport communication functions to connect the S7-200 CPUs to many devices that are compatible with the RS-232 standard. There are two different types of PC/PPI cables: An isolated PC/PPI cable with an RS-232 port that has 5 DIP switches for setting baud rate and other configuration items (see Figure 7-26).
Setting Up Communications Hardware and Network Communications If you are using the PC/PPI cable in a system where Freeport communication is used, the turnaround time must be comprehended by the user program in the S7-200 CPU for the following situations: The S7-200 CPU responds to messages transmitted by the RS-232 device.
Setting Up Communications Hardware and Network Communications Using a Modem with a 5-Switch PC/PPI Cable You can use the 5-switch PC/PPI cable to connect the RS-232 communication port of a modem to an S7-200 CPU. Modems normally use the RS-232 control signals (such as RTS, CTS, and DTR) to allow a PC to control the modem. The PC/PPI cable does not monitor any of these signals, but does provide RTS in DTE mode.
Setting Up Communications Hardware and Network Communications To set the mode to Data Communications Equipment (DCE), you should set switch 5 to the 0 or down position (see Figure 7-26). To set the mode to Data Terminal Equipment (DTE), you should set switch 5 to the 1 or up position. Table 7-9 shows the pin numbers and functions for the RS-485 to RS-232 port of the PC/PPI cable in DTE mode. Table 7-10 shows the pin numbers and functions for the RS-485 to RS-232 port of the PC/PPI cable in DCE mode.
Setting Up Communications Hardware and Network Communications Switch 4 of the PC/PPI cable tells the S7-200 CPU to use either a 10-bit protocol or the normal 11-bit PPI protocol. This switch setting has no use if the CPU is not connected to STEP 7-Micro/WIN 32 and should be left in the 11-bit setting for proper operation with other devices.
Setting Up Communications Hardware and Network Communications Using a Modem with a 4-Switch PC/PPI Cable You can use a 4-switch PC/PPI cable to connect the RS-232 communication port of a modem to an S7-200 CPU. Modems normally use the RS-232 control signals (such as RTS, CTS, and DTR) to allow a PC to control the modem. This PC/PPI cable does not use any of these signals, so when you use a modem with a 4-switch PC/PPI cable, the modem must be configured to operate without these signals.
Setting Up Communications Hardware and Network Communications 7.8 Network Performance Optimizing Network Performance The two factors which have the greatest effect on network performance are the baud rate and the number of masters. Operating the network at the highest baud rate supported by all devices has the greatest effect on the network. Minimizing the number of masters on a network also increases the performance of the network.
Setting Up Communications Hardware and Network Communications As a general rule, you should set the highest station address on all masters to the same value. This address should be greater than or equal to the highest master address. The S7-200 CPUs default to a value of 31 for the highest station address. Token Rotation In a token-passing network, the station that holds the token is the only station that has the right to initiate communication.
Setting Up Communications Hardware and Network Communications In this configuration, the TD 200 (station 3) communicates with the CPU 222 (station 2), TD 200 (station 5) communicates with CPU 222 (station 4), and so on. Also, CPU 224 (station 6) is sending messages to stations 2, 4, and 8, and CPU 224 (station 8) is sending messages to stations 2, 4, and 6. In this network, there are six master stations (the four TD 200 units and the two CPU 224 modules) and two slave stations (the two CPU 222 modules).
Setting Up Communications Hardware and Network Communications Token Rotation Time The token rotation time is determined by how long each station holds the token. You can determine the token rotation time for your S7-200 multiple-master network by adding the times that each master holds the token. If the PPI master mode has been enabled (under the PPI protocol on your network), you can send messages to other CPUs by using the Network Read (NETR) and Network Write (NETW) instructions with the CPU.
Setting Up Communications Hardware and Network Communications Token Rotation Comparison Table 7-11, Table 7-12, and Table 7-13 show comparisons of the token rotation time versus the number of stations and amount of data at 9.6 kbaud, 19.2 kbaud, and 187.5 kbaud, respectively. The times are figured for a case where you use the Network Read (NETR) and Network Write (NETW) instructions with the CPU or other master devices. Table 7-11 Token Rotation Time versus Number of Stations and Amount of Data at 9.
Setting Up Communications Hardware and Network Communications Table 7-12 Token Rotation Time versus Number of Stations and Amount of Data at 19.2 kbaud Bytes Transferred per Station at 19.2 kbaud Number of Stations, with Time in Seconds 2 stations 3 stations 4 stations 5 stations 6 stations 7 stations 8 stations 9 stations 10 stations 1 0.15 0.22 0.30 0.37 0.44 0.52 0.59 0.67 0.74 2 0.15 0.22 0.30 0.37 0.45 0.52 0.60 0.67 0.74 3 0.15 0.23 0.30 0.38 0.45 0.53 0.60 0.
Conventions for S7-200 Instructions 8 The following conventions are used in this chapter to illustrate the equivalent ladder logic, function block diagram, and statement list instructions and the CPUs in which the instructions are available. Chapter Overview Section Description Page 8.1 Concepts and Conventions for STEP 7-Micro/WIN 32 Programming 8-2 8.
Conventions for S7-200 Instructions 8.1 Concepts and Conventions For STEP 7-Micro/WIN 32 Programming The following diagram shows the Micro/WIN 32 instruction format as used throughout this chapter. A description of the components of the instruction format follows the diagram. Add Integer and Subtract Integer L A D ADD_I ENO EN F B D IN1 OUT OUT The Add Integer and Subtract Integer instructions add or subtract two 16-bit integers and produce a 16-bit result (OUT).
Conventions for S7-200 Instructions Title of the Instruction or Instruction Group: In this example Add Integer and Subtract Integer is the title. Figure Showing the Micro/WIN 32 Instruction: The figure below the instruction title contains a picture of the LAD instruction element, the FBD instruction element and for SIMATIC instructions, the STL instruction mnemonics and operands.
Conventions for S7-200 Instructions Operand Table: Beneath the LAD/FBD/STL figure is a table that lists the allowed operands for each of the inputs and outputs, along with the data types of each operand. The memory ranges of the operands for each CPU are shown in Table 8-3. EN/ENO operands and data types are not shown in the instruction operand table because the operands are the same for all LAD and FBD instructions. Table 8-1 lists these operands and data types for LAD and FBD.
Conventions for S7-200 Instructions In SIMATIC STL, there is no ENO output, but the STL instructions that correspond to the LAD and FBD instructions with ENO outputs do set a special ENO bit. This bit is accessible with the STL instruction AENO (AND ENO), and may be used to generate the same effect as the ENO bit of a box. Conditional/Unconditional Inputs: In LAD and FBD, a box or a coil that is dependent upon power flow is shown without a connection to any element on the left side.
Conventions for S7-200 Instructions STEP 7-Micro/WIN 32 Conventions: In STEP 7-Micro/WIN 32, the following conventions apply: The ladder editor symbol “--->” is an optional power flow connection. The ladder editor symbol “--->>” is a required power flow connection. Double quotes around a symbol name “var1” indicate that the symbol is of global scope. The pound character in front of a symbol name #var1 indicates that the symbol is of local scope.
Conventions for S7-200 Instructions 8.
Conventions for S7-200 Instructions Table 8-3 S7-200 CPU Operand Ranges Access Method Bit access (byte.bit) Byte access Word access Double word access CPU 221 CPU 224 V 0.0 to 2047.7 V 0.0 to 2047.7 V 0.0 to 5119.7 I 0.0 to 15.7 I 0.0 to 15.7 I 0.0 to 15.7 Q 0.0 to 15.7 Q 0.0 to 15.7 Q 0.0 to 15.7 M 0.0 to 31.7 M 0.0 to 31.7 M 0.0 to 31.7 SM 0.0 to 179.7 SM 0.0 to 179.7 SM 0.0 to 179.7 S 0.0 to 31.7 S 0.0 to 31.7 S 0.0 to 31.
9 SIMATIC Instructions This chapter describes the SIMATIC instruction set for the S7-200. Chapter Overview Section Description Page 9.1 SIMATIC Bit Logic Instructions 9-2 9.2 SIMATIC Compare Instructions 9-10 9.3 SIMATIC Timer Instructions 9-15 9.4 SIMATIC Counter Instructions 9-23 9.5 SIMATIC High-Speed Counter Instructions 9-27 9.6 SIMATIC Pulse Output Instructions 9-49 9.7 SIMATIC Clock Instructions 9-70 9.8 SIMATIC Integer Math Instructions 9-72 9.
SIMATIC Instructions 9.1 SIMATIC Bit Logic Instructions Standard Contacts L A D bit bit The Normally Open contact is closed (on) when the bit is equal to 1. / F B D These instructions obtain the referenced value from the memory or process-image register if the data type is I or Q. You can use a maximum of seven inputs to both the AND and the OR boxes. AND The Normally Closed contact is closed (on) when the bit is equal to 0.
SIMATIC Instructions Immediate Contacts L A D bit I The immediate instruction obtains the physical input value when the instruction is executed, but the process-image register is not updated. bit /I The Normally Open Immediate contact is closed (on) when the physical input point (bit) is 1. The Normally Closed Immediate contact is closed (on) when the physical input point (bit) is 0. F B D In LAD, normally open and normally closed immediate instructions are represented by contacts.
SIMATIC Instructions Not L A D NOT F B D In LAD, the NOT instruction is shown as a contact. L A D S T L The NOT contact changes the state of power flow. When power flow reaches the Not contact, it stops. When power flow does not reach the Not contact, it supplies power flow. In FBD, the NOT instruction uses the graphical negation symbol with Boolean box inputs. In STL, the NOT instruction changes the value on the top of the stack from 0 to 1, or from 1 to 0.
SIMATIC Instructions Contact Examples LAD Network 1 I0.0 I0.1 STL NETWORK 1 LD I0.0 A I0.1 = Q0.0 Q0.0 Network 2 I0.0 NETWORK 2 LD I0.0 NOT = Q0.1 Q0.1 NOT Network 3 I0.1 NETWORK 3 LD I0.1 ED = Q0.2 Q0.2 N FBD Network 1 AND I0.0 Q0.0 I0.1 Network 2 Q0.1 = I0.0 Network 3 N I0.1 IN OUT Q0.2 Timing Diagram I0.0 I0.1 Q0.0 Q0.1 On for one scan Q0.
SIMATIC Instructions Output L A D bit When the Output instruction is executed, the output bit in the process image register is turned on. In LAD and FBD, when the output instruction is executed, the specified bit is set to equal to power flow. F B D bit = S T L In STL, the output instruction copies the top of the stack to the specified bit.
SIMATIC Instructions Set, Reset (N Bits) bit S N bit R N L A D F B D bit When the Set and Reset instructions are executed, the specified number of points (N) starting at the value specified by the bit or OUT parameter are set (turned on) or reset (turned off). The range of points that can be set or reset is 1 to 255. When using the Reset instruction, if the bit is specified to be either a T- or C-bit, then either the timer or counter bit is reset and the timer/counter current value is cleared.
SIMATIC Instructions Set Immediate, Reset Immediate (N Bits) L A D bit SI N bit RI N bit F B D SI EN N bit RI EN The range of points that can be set or reset is 1 to 128. The “I” indicates an immediate reference; the new value is written to both the physical output point and the corresponding process-image register location when the instruction is executed. This differs from the non-immediate references, which write the new value to the process-image register only.
SIMATIC Instructions Output Examples LAD Network 1 I0.0 STL NETWORK 1 LD I0.0 = Q0.0 S Q0.1, 1 R Q0.2, 2 Q0.0 Q0.1 S 1 Q0.2 R 2 FBD Network 1 Q0.0 = AND I0.0 SM0.0 Q0.1 S EN 1 N Q0.2 R EN 2 N Timing Diagram I0.0 Q0.0 Q0.1 Q0.2 Q0.
SIMATIC Instructions 9.2 SIMATIC Compare Instructions Compare Byte L A D IN1 ==B IN2 The Compare Byte instruction is used to compare two values: IN1 to IN2. Comparisons include: IN1 = IN2, IN1 >= IN2, IN1 <= IN2, IN1 > IN2, IN1 < IN2, or IN1 <> IN2. Byte comparisons are unsigned. F B D ==B In LAD, the contact is on when the comparison is true. In FBD, the output is on when the comparison is true. In STL, the instructions Load, AND, or OR, a 1 with the top of stack when the comparison is true.
SIMATIC Instructions Compare Integer L A D IN1 ==I IN2 The Compare Integer instruction is used to compare two values: IN1 to IN2. Comparisons include: IN1 = IN2, IN1 >= IN2, IN1 <= IN2, IN1 > IN2, IN1 < IN2, or IN1 <> IN2. Integer comparisons are signed (16#7FFF > 16#8000). F B D ==I In LAD, the contact is on when the comparison is true. In FBD, the output is on when the comparison is true. In STL, the instructions Load, AND, or OR a 1 with the top of stack when the comparison is true.
SIMATIC Instructions Compare Double Word L A D IN1 ==D IN2 The Compare Double Word instruction is used to compare two values: IN1 to IN2. Comparisons include: IN1 = IN2, IN1 >= IN2, IN1 <= IN2, IN1 > IN2, IN1 < IN2, or IN1 <> IN2. Double word comparisons are signed (16#7FFFFFFF > 16#80000000). F B D ==D In LAD, the contact is on when the comparison is true. In FBD, the output is on when the comparison is true.
SIMATIC Instructions Compare Real L A D IN1 ==R IN2 Compare Real instruction is used to compare two values: IN1 to IN2. Comparisons include: IN1 = IN2, IN1 >= IN2, IN1 <= IN2, IN1 > IN2, IN1 < IN2, or IN1 <> IN2. Real comparisons are signed. F B D ==R In LAD, the contact is on when the comparison is true. In FBD, the output is on when the comparison is true. In STL, the instructions Load, AND, or OR a 1 with the top of stack when the comparison is true.
SIMATIC Instructions Comparison Contact Examples LAD Network 4 VW4 >=I VW8 STL NETWORK 4 LDW>= VW4, VW8 = Q0.3 Q0.3 FBD Network 4 >=I VW4 Q0.3 VW8 Timing Diagram VW4 >= VW8 VW4 < VW8 Q0.
SIMATIC Instructions 9.3 SIMATIC Timer Instructions On-Delay Timer, Retentive On-Delay Timer, Off-Delay Timer L A D Txxx TON IN F B D PT Txxx TONR IN PT Txxx TOF IN The On-Delay timer current value is cleared when the enabling input is OFF, while the current value of the Retentive On-Delay Timer is maintained when the input is OFF. You can use the Retentive On-Delay Timer to accumulate time for multiple periods of the input ON.
SIMATIC Instructions TON, TONR, and TOF timers are available in three resolutions. The resolution is determined by the timer number as shown in Table 9-1. Each count of the current value is a multiple of the time base. For example, a count of 50 on a 10-ms timer represents 500 ms. Table 9-1 Timer Numbers and Resolutions Timer Type TONR TON, TOF Resolution in milliseconds (ms) Maximum Value in seconds (s) Timer Number 1 ms 32.767 s T0, T64 10 ms 327.67 s T1 to T4, T65 to T68 100 ms 3276.
SIMATIC Instructions Understanding the S7-200 Timer Instructions You can use timers to implement time-based counting functions. The S7-200 instruction set provides three types of timers as shown below. Table 9-2 shows the actions of the different timers.
SIMATIC Instructions The actions of the timers at different resolutions are explained below. 1-Millisecond Resolution The 1-ms timers count the number of 1-ms timer intervals that have elapsed since the active 1-ms timer was enabled. The execution of the timer instruction starts the timing; however, the 1-ms timers are updated (timer bit and timer current) every millisecond asynchronous to the scan cycle.
SIMATIC Instructions Updating the Timer Current Value The effect of the various ways in which current time values are updated depends upon how the timers are used. For example, consider the timer operation shown in Figure 9-4. In the case where the 1-ms timer is used, Q0.0 is turned on for one scan whenever the timer’s current value is updated after the normally closed contact T32 is executed and before the normally open contact T32 is executed. In the case where the 10-ms timer is used, Q0.
SIMATIC Instructions On-Delay Timer Example LAD I2.0 IN 3 FBD T33 TON T33 TON PT I2.0 IN 3 PT STL LD TON I2.0 T33, 3 Timing Diagram I2.
SIMATIC Instructions Retentive On-Delay Timer Example LAD I2.1 IN 10 FBD T2 TONR T2 TONR PT I2.1 IN 10 PT STL LD TONR I2.1 T2, 10 Timing Diagram I2.
SIMATIC Instructions Off-Delay Timer Example LAD I0.0 IN 3 FBD T33 TOF I0.0 3 PT T33 TOF IN PT STL LD TOF I0.0 T33, 3 Timing Diagram I0.
SIMATIC Instructions 9.4 SIMATIC Counter Instructions Count Up, Count Up/Down, Count Down L A D Cxxx CU CTU F B D R The Count Up instruction counts up to the maximum value on the rising edges of the Count Up (CU) input. When the current value (Cxxx) is greater than or equal to the Preset Value (PV), the counter bit (Cxxx) turns on. The counter is reset when the Reset (R) input turns on.
SIMATIC Instructions Understanding the S7-200 Counter Instructions The Up Counter (CTU) counts up from the current value of that counter each time the count-up input makes the transition from off to on. The counter is reset when the reset input turns on, or when the Reset instruction is executed. The counter stops upon reaching the maximum value (32,767).
SIMATIC Instructions Counter Examples LAD FBD C50 I3.0 C50 CTD CD I3.0 CD I1.0 LD 3 PV CTD I1.0 LD PV 3 STL LD LD CTD I3.0 I1.0 C50, 3 //Count Down Input //Load Input Timing Diagram I3.0 Down I1.
SIMATIC Instructions LAD I4.0 CU FBD C48 CTUD I4.0 CU I3.0 CD I2.0 R C48 CTUD I3.0 CD I2.0 R 4 4 PV PV STL LD LD LD CTUD I4.0 I3.0 I2.0 C48, 4 //Count Up Input //Count Down Input //Reset Input Timing Diagram I4.0 Up I3.0 Down I2.
SIMATIC Instructions 9.5 SIMATIC High-Speed Counter Instructions High-Speed Counter Definition, High-Speed Counter L A D HDEF EN ENO HSC MODE EN HSC ENO The High-Speed Counter Definition instruction assigns a MODE to the referenced high-speed counter (HSC). See Table 9-5. The High-Speed Counter instruction, when executed, configures and controls the operational mode of the high-speed counter, based on the state of the HSC special memory bits. The parameter N specifies the high-speed counter number.
SIMATIC Instructions Using the High-Speed Counter Typically, a high-speed counter is used as the drive for a drum timer, where a shaft rotating at a constant speed is fitted with an incremental shaft encoder. The shaft encoder provides a specified number of counts per revolution and a reset pulse that occurs once per revolution. The clock(s) and the reset pulse from the shaft encoder provide the inputs to the high-speed counter.
SIMATIC Instructions Reset interrupt generated Counter Disabled Start (Active High) 1 0 Reset (Active High) 1 0 Counter Enabled Counter Disabled Reset interrupt generated Counter Enabled +2,147,483,647 Counter Current Value Current value frozen 0 Current value frozen -2,147,483,648 Counter value is somewhere in this range. Figure 9-11 Operation Example with Reset and Start Current value loaded to 0, preset loaded to 4, counting direction set to Up. Counter enable bit set to enabled.
SIMATIC Instructions Current value loaded to 0, preset loaded to 4, counting direction set to Up. Counter enable bit set to enabled. PV=CV interrupt generated PV=CV interrupt generated and Direction Changed interrupt generated 1 0 Clock 1 External Direction Control (1 = Up) 0 5 4 4 3 3 2 Counter Current Value 2 1 1 0 Figure 9-13 Operation Example of Modes 3, 4, or 5 When you use counting modes 6, 7, or 8 and a rising edge on both the up clock and down clock inputs occurs within 0.
SIMATIC Instructions Current value loaded to 0, preset loaded to 3, initial counting direction set to Up. Counter enable bit set to enabled. PV=CV interrupt generated and Direction Changed interrupt generated PV=CV interrupt generated Phase A 1 Clock 0 Phase B 1 Clock 0 4 3 3 2 Counter Current Value 0 Figure 9-15 2 1 Operation Example of Modes 9, 10, or 11 (Quadrature 1x Mode) Current value loaded to 0, preset loaded to 9, initial counting direction set to Up. Counter enable bit set to enabled.
SIMATIC Instructions Connecting the Input Wiring for the High-Speed Counters Table 9-3 shows the inputs used for the clock, direction control, reset, and start functions associated with the high-speed counters. These input functions and the HSC modes of operation are described in Table 9-5 through Table 9-10. Table 9-3 Dedicated Inputs for High-Speed Counters Inputs Used High-Speed Counter HSC0 I0.0, I0.1, 0.2 HSC1 I0.6, I0.7, I1.0, I1.1 HSC2 I1.2, I1.3, I1.4, I1.5 HSC3 I0.1 HSC4 I0.3, I0.4, I0.
SIMATIC Instructions Table 9-4 Input Point Assignments for High-Speed Counters and Edge Interrupts Input Point (I) Element HSC0 0.0 x 0.1 x 0.2 0.3 0.4 0.5 0.6 0.7 1.0 1.1 x x x 1.4 1.5 x HSC2 x HSC3 1.3 x HSC1 x x x x HSC4 x HSC5 x x x Edge Interrupts Table 9-5 1.2 x x x x HSC0 Modes of Operation HSC0 Mode 0 1 3 4 6 Description 10 I0.1 I0.2 Single phase up/down counter with internal direction control SM37.3 SM37 3 = 0, 0 count down SM37.
SIMATIC Instructions Table 9-6 HSC1 Modes of Operation HSC1 Mode 0 1 Description I0.6 I0.7 I1.0 Single phase up/down counter with internal direction control Clock SM47.3 = 0, count down SM47.3 = 1, count u up Reset 2 3 4 5 6 7 Start Single phase up/down counter with external direction control Cl k Clock I0.7 = 0, count down I0 7 = 1, I0.7 1 count up Di Dir.
SIMATIC Instructions Table 9-8 HSC3 Modes of Operation HSC3 Mode 0 Description I0.1 Single phase up/down counter with internal direction control Clock SM137.3 = 0, count down SM137.3 = 1, count up Table 9-9 HSC4 Modes of Operation HSC4 Mode 0 1 3 4 6 7 9 10 Description I0.3 I0.4 I0.5 Single phase up/down counter with internal direction control Clock SM147.3 SM147 3 = 0, 0 count down SM147.3 = 1, count up Reset Single phase up/down counter with external direction control Dir. Clock I0.
SIMATIC Instructions Addressing the High-Speed Counters (HC) To access the count value for the high-speed counter, you specify the address of the high-speed counter, using the memory type (HC) and the counter number (such as HC0). The current value of the high-speed counter is a read-only value and can be addressed only as a double word (32 bits), as shown in Figure 9-17.
SIMATIC Instructions Selecting the Active State and 1x/4x Mode Four counters have three control bits that are used to configure the active state of the reset and start inputs and to select 1x or 4x counting modes (quadrature counters only). These bits are located in the control byte for the respective counter and are only used when the HDEF instruction is executed. These bits are defined in Table 9-11. You must set these control bits to the desired state before the HDEF instruction is executed.
SIMATIC Instructions Control Byte Once you have defined the counter and the counter mode, you can program the dynamic parameters of the counter. Each high-speed counter has a control byte that allows the counter to be enabled or disabled; the direction to be controlled (modes 0, 1, and 2 only), or the initial counting direction for all other modes; the current value to be loaded; and the preset value to be loaded.
SIMATIC Instructions Table 9-13 Current and Preset Values of HSC0, HSC1, HSC2, HSC3, HSC4, and HSC5 Value to be Loaded HSC0 HSC1 HSC2 HSC3 HSC4 HSC5 New current SMD38 SMD48 SMD58 SMD138 SMD148 SMD158 New preset SMD42 SMD52 SMD62 SMD142 SMD152 SMD162 Status Byte A status byte is provided for each high-speed counter that provides status memory bits that indicate the current counting direction, and whether the current value is greater or equal to the preset value.
SIMATIC Instructions HSC Interrupts All counter modes support an interrupt on current value equal to the preset value. Counter modes that use an external reset input support an interrupt on external reset activated. All counter modes except modes 0, 1, and 2 support an interrupt on a counting direction change. Each of these interrupt conditions may be enabled or disabled separately. For a complete discussion on the use of interrupts, see Section 9.16.
SIMATIC Instructions Initialization Modes 0, 1, or 2 The following steps describe how to initialize HSC1 for Single Phase Up/Down Counter with Internal Direction (Modes 0, 1, or 2): 1. Use the first scan memory bit to call a subroutine in which the initialization operation is performed. Since you use a subroutine call, subsequent scans do not make the call to the subroutine, which reduces scan time execution and provides a more structured program. 2.
SIMATIC Instructions Initialization Modes 3, 4, or 5 The following steps describe how to initialize HSC1 for Single Phase Up/Down Counter with External Direction (Modes 3, 4, or 5): 1. Use the first scan memory bit to call a subroutine in which the initialization operation is performed. Since you use a subroutine call, subsequent scans do not make the call to the subroutine, which reduces scan time execution and provides a more structured program. 2.
SIMATIC Instructions Initialization Modes 6, 7, or 8 The following steps describe how to initialize HSC1 for Two Phase Up/Down Counter with Up/Down Clocks (Modes 6, 7, or 8): 1. Use the first scan memory bit to call a subroutine in which the initialization operations are performed. Since you use a subroutine call, subsequent scans do not make the call to the subroutine, which reduces scan time execution and provides a more structured program. 2.
SIMATIC Instructions Initialization Modes 9, 10, or 11 The following steps describe how to initialize HSC1 for A/B Phase Quadrature Counter (Modes 9, 10, or 11): 1. Use the first scan memory bit to call a subroutine in which the initialization operations are performed. Since you use a subroutine call, subsequent scans do not make the call to the subroutine, which reduces scan time execution and provides a more structured program. 2.
SIMATIC Instructions Change Direction in Modes 0, 1, or 2 The following steps describe how to configure HSC1 for Change Direction for Single Phase Counter with Internal Direction (Modes 0, 1, or 2): 1. Load SMB47 to write the desired direction: SMB47 = 16#90 Enables the counter Sets the direction of the HSC to count down SMB47 = 16#98 Enables the counter Sets the direction of the HSC to count up 2. Execute the HSC instruction to cause the S7-200 to program HSC1.
SIMATIC Instructions Load a New Preset Value (Any Mode) The following steps describe how to change the preset value of HSC1 (any mode): 1. Load SMB47 to write the desired preset value: SMB47 = 16#A0 Enables the counter Writes the new preset value 2. Load SMD52 (double word size value) with the desired preset value. 3. Execute the HSC instruction to cause the S7-200 to program HSC1.
SIMATIC Instructions High-Speed Counter Example LAD STL MAIN OB1 Network 1 SM0.1 On the first scan, call subroutine 0. SBR0 EN Network 1 LD SM0.1 CALL 0 End of main program. SUBROUTINE 0 Network 1 SM0.0 16#F8 EN MOV_B ENO IN OUT HDEF EN ENO 1 HSC 11 MODE Enable the counter. Write a new current value. Write a new preset value. Set initial direction to count SMB47 up. Set start and reset inputs to be active high. Set 4x mode. HSC1 configured for quadrature mode with reset and start inputs.
SIMATIC Instructions FBD MAIN OB1 Network 1 SM0.1 On the first scan, call subroutine 0. SBR0 EN End of main program. SUBROUTINE 0 Network 1 SM0.0 1 11 HDEF EN ENO HSC MODE 0 ATCH EN ENO INT MOV_B EN ENO 16#F8 IN OUT SMB47 MOV_DW EN ENO 50 IN OUT SMD52 13 MOV_DW EN ENO 0 IN 1 EN N OUT SMD48 HSC ENO EVENT ENI INTERRUPT 0 Network 1 SM0.
SIMATIC Instructions 9.6 SIMATIC Pulse Output Instructions Pulse Output L A D PLS EN ENO F B D Q The Pulse Output instruction examines the special memory bits for the pulse output (Q0.0 or Q0.1). The pulse operation defined by the special memory bits is then invoked. Operands: S T L PLS Q 3 3 3 221 222 224 Q Constant (0 or 1) Data Types: WORD Pulse Output Ranges Q0.0 through Q0.
SIMATIC Instructions You can change the characteristics of a PTO or PWM waveform by modifying the desired locations in the SM area (including the control byte), and then executing the PLS instruction. You can disable the generation of a PTO or PWM waveform at any time by writing zero to the PTO/PWM enable bit of the control byte (SM67.7 or SM77.7), and then executing the PLS instruction. Note Default values for all control bits, cycle time, pulse width, and pulse count values are zero.
SIMATIC Instructions The PWM Update Method bit (SM67.4 or SM77.4) in the control byte is used to specify the update type. Execute the PLS instruction to invoke the changes. Be aware that if the time base is changed, an asynchronous update will occur regardless of the state of the PWM Update Method bit. PTO Operation The PTO function provides for the generation of a square wave (50% duty cycle) pulse train with a specified number of pulses.
SIMATIC Instructions Single Segment Pipelining In single segment pipelining, you are responsible for updating the SM locations for the next pulse train. Once the initial PTO segment has been started, you must modify immediately the SM locations as required for the second waveform, and execute the PLS instruction again. The attributes of the second pulse train will be held in a pipeline until the first pulse train is completed. Only one entry at a time can be stored in the pipeline.
SIMATIC Instructions The format of the profile table is shown in Table 9-15. An additional feature available with multiple segment PTO operation is the ability to increase or decrease the cycle time automatically by a specified amount for each pulse. Programming a positive value in the cycle time delta field increases cycle time. Programming a negative value in the cycle time delta field decreases cycle time. A value of zero results in an unchanging cycle time.
SIMATIC Instructions Calculating Profile Table Values The multiple segment pipelining capability of the PTO/PWM generators can be useful in many applications, particularly in stepper motor control. The example shown in Figure 9-20 illustrates how to determine the profile table values required to generate an output waveform that accelerates a stepper motor, operates the motor at a constant speed, and then decelerates the motor.
SIMATIC Instructions Assuming that the profile table is located in V memory starting at V500, the table values used to generate the desired waveform are shown in Table 9-16.
SIMATIC Instructions The duration of a given profile segment can be useful in the process of determining correct profile table values.
SIMATIC Instructions Table 9-17 PTO /PWM Control Registers Q0.0 Q0.1 Status Byte SM66.4 SM76.4 PTO profile aborted due to delta calculation error 0 = no error; 1 = aborted SM66.5 SM76.5 PTO profile aborted due to user command 0 = no abort; 1 = aborted SM66.6 SM76.6 PTO pipeline overflow/underflow 0 = no overflow; 1 = overflow/underflow SM66.7 SM76.7 PTO idle Q0.0 Q0.1 SM67.0 SM77.0 PTO/PWM update cycle time value 0 = no update; 1 = update cycle time SM67.1 SM77.
SIMATIC Instructions Table 9-18 PTO/PWM Control Byte Reference Result of executing the PLS instruction Control Register (Hex Enable Value) Select Mode PTO Segment Operation 16#81 Yes PTO Single 1 µs/cycle 16#84 Yes PTO Single 1 µs/cycle Load 16#85 Yes PTO Single 1 µs/cycle Load 16#89 Yes PTO Single 1 ms/cycle 16#8C Yes PTO Single 1 ms/cycle Load 16#8D Yes PTO Single 1 ms/cycle Load 16#A0 Yes PTO Multiple 1 µs/cycle 16#A8 Yes PTO Multiple 1 ms/cycle 16#D1 Yes
SIMATIC Instructions PWM Initialization To initialize the PWM for Q0.0, follow these steps: 1. Use the first scan memory bit (SM0.1) to initialize the output to 0, and call the subroutine that you need in order to perform the initialization operations. When you use the subroutine call, subsequent scans do not make the call to the subroutine. This reduces scan time execution and provides a more structured program. 2.
SIMATIC Instructions PTO Initialization - Single Segment Operation To initialize the PTO, follow these steps: 1. Use the first scan memory bit (SM0.1) to initialize the output to 0, and call the subroutine that you need to perform the initialization operations. This reduces scan time execution and provides a more structured program. 2. In the initialization subroutine, load SMB67 with a value of 16#85 for PTO using microsecond increments (or 16#8D for PTO using millisecond increments).
SIMATIC Instructions Changing the PTO Pulse Count - Single Segment Operation To change the PTO Pulse Count in an interrupt routine or a subroutine when using single segment PTO operation, follow these steps: 1. Load SMB67 with a value of 16#84 for PTO using microsecond increments (or 16#8C for PTO using millisecond increments). These values set the control byte to enable the PTO/PWM function, select PTO operation, select either microsecond or millisecond increments, and set the update pulse count value. 2.
SIMATIC Instructions PTO Initialization - Multiple Segment Operation To initialize the PTO, follow these steps: 1. Use the first scan memory bit (SM0.1) to initialize the output to 0, and call the subroutine that you need to perform the initialization operations. This reduces the scan time execution and provides a more structured program. 2. In the initialization subroutine, load SMB67 with a value of 16#A0 for PTO using microsecond increments (or 16#A8 for PTO using millisecond increments).
SIMATIC Instructions Example of Pulse Width Modulation Figure 9-21 shows an example of the Pulse Width Modulation. LAD STL MAIN OB1 Network 1 SM0.1 Q0.1 R 1 On the first scan, set image register bit low, and call subroutine 0. SBR0 Network 2 When pulse width change to 50% duty cycle is required, M0.0 is set. M0.0 P SBR1 . . End of main ladder. Network 1 LD SM0.1 R Q0.1, 1 CALL 0 Network 2 LD M0.0 EU CALL 1 . . SUBROUTINE 0 Start of subroutine 0. Network 1 SM0.
SIMATIC Instructions FBD MAIN OB1 Network 1 Q0.1 AND R EN SM0.1 1 SM0.0 N SBR0 EN Network 2 AND P M0.0 IN SBR1 EN OUT SM0.0 SUBROUTINE 0 Network 1 SM0.0 MOV_B EN ENO 16#DB IN OUT MOV_W SMB77 10000 MOV_W EN ENO IN OUT SMW78 1000 EN ENO IN OUT PLS EN SMW80 1 MOV_B ENO Q0.x 16#DA EN ENO IN OUT SMB77 SUBROUTINE 1 Network 61 SM0.0 5000 MOV_W EN ENO IN OUT EN SMW80 1 PLS ENO Q0.X Timing Diagram Q0.
SIMATIC Instructions Example of Pulse Train Output Using Single Segment Operation LAD STL MAIN MAIN OB1 OB1 Network 1 Q0.0 R 1 SM0.1 On the first scan, reset image register bit low, and call subroutine 0. SBR0 EN Network 1 LD SM0.1 R Q0.0, 1 CALL 0 SUBROUTINE 0 Network 1 Set up control byte: - select PTO operation - select ms increments SMB67- set the pulse count and cycle time values - enable the PTO function MOV_B EN ENO SM0.0 16#8D IN OUT MOV_W EN ENO 500 Set cycle time to 500 ms.
SIMATIC Instructions LAD STL INTERRUPT 3 Network 1 SMW68 ==I 500 MOV_W EN ENO 1000 IN OUT EN PLS ENO If current cycle time is 500 ms, then set cycle time of 1000 ms SMW68 and output 4 pulses. Network LDW= MOVW PLS CRETI 1 SMW68, 500 1000, SMW68 0 If current cycle time is 1000 ms, then set cycle time of 500 ms SMW68 and output 4 pulses. Network LDW= MOVW PLS 2 SMW68, 1000 500, SMW68 0 0 Q RETI Network 2 SMW68 ==I 1000 MOV_W EN ENO 500 IN EN OUT PLS ENO 0 Q0.
SIMATIC Instructions FBD MAIN OB1 Network 1 Q0.0 R SM0.1 EN 1 IN SBR0 EN ENO SUBROUTINE 0 Network 1 MOV_B SM0.0 16#8D EN IN EN 3 MOV_DW MOV_W ENO OUT SMB67 EN 500 IN ATCH ENO ENO OUT 4 SMW68 EN ENO IN OUT SMD72 ENI INT 19 EVNT EN 0 PLS ENO Q0.X MOV_B EN ENO 16#89 IN OUT SMB67 INTERRUPT 3 Network 1 ==I MOV_W EN ENO SMW68 1000 500 IN OUT EN SMW68 PLS ENO RETI 0 Q0.x Network 2 ==I SMW68 1000 500 MOV_W EN ENO IN OUT SMW68 EN 0 PLS ENO Q0.
SIMATIC Instructions Example of Pulse Train Output Using Multiple Segment Operation LAD STL MAIN MAIN OB1 OB1 Network 1 Q0.0 R 1 SM0.1 On the first scan, reset image register bit low, and call subroutine 0. SBR0 EN Network 1 LD SM0.1 R Q0.0, 1 CALL 0 SUBROUTINE 0 Network 1 MOV_B EN ENO SM0.0 16#AO IN OUT SMB67 MOV_W EN ENO 500 IN OUT Specify that the start address of the profile table is V500. IN OUT Set number of profile table segments to 3.
SIMATIC Instructions LAD Network 1 MOV_W EN ENO 100 IN OUT VW509 MOV_W EN ENO 0 IN OUT Set the delta cycle time for segment #2 to 0 µs. VW511 MOV_D EN ENO 3400 IN OUT IN OUT 100, VW509 0, VW511 3400, VD513 100, VW517 1, VW519 400, VD521 2, 19 0 VD513 Set the initial cycle time for segment #3 to 100 µs. VW517 MOV_W EN ENO 1 MOVW MOVW MOVD MOVW MOVW MOVD ATCH ENI PLS Set the number of pulses in segment #2 to 3400. MOV_W EN ENO 100 IN OUT Set the initial cycle time for segment #2 to 100 µs.
SIMATIC Instructions 9.7 SIMATIC Clock Instructions Read Real-Time Clock, Set Real-Time Clock L A D READ_RTC EN ENO F B D T SET_RTC EN ENO The Set Real-Time Clock instruction writes the current time and date loaded in an 8-byte buffer (starting at address T) to the clock. In STL, the TODR and TODW instructions are represented as Time of Day Read (TODR) and Time of Day Write (TODW).
SIMATIC Instructions The time-of-day clock initializes the following date and time after extended power outages or memory has been lost: Date: Time: Day of Week 01-Jan-90 00:00:00 Sunday The time-of-day clock in the S7-200 uses only the least significant two digits for the year, so for the year 2000, the year will be represented as 00 (it will go from 99 to 00). You must code all date and time values in BCD format (for example, 16#97 for the year 1997).
SIMATIC Instructions 9.8 SIMATIC Integer Math Instructions Add Integer and Subtract Integer L A D ADD_I ENO EN F B D IN1 OUT OUT The Add Integer and Subtract Integer instructions add or subtract two 16-bit integers and produce a 16-bit result (OUT). In LAD and FBD: IN1 + IN2 = OUT IN1 - IN2 = OUT In STL: IN1 + OUT = OUT OUT - IN1 = OUT IN2 SUB_I EN ENO IN1 OUT OUT IN2 S T L Inputs/Outputs Error conditions that set ENO = 0: SM1.1 (overflow), SM4.
SIMATIC Instructions Add Double Integer and Subtract Double Integer L A D F B D ADD_DI EN ENO The Add Double Integer and Subtract Double Integer instructions add or subtract two 32-bit integers, and produce a 32-bit result (OUT). IN1 OUT OUT In LAD and FBD: IN1 + IN2 = OUT IN1 - IN2 = OUT In STL: IN1 + OUT = OUT OUT - IN1 = OUT IN2 SUB_DI EN ENO IN1 OUT OUT IN2 S T L Error conditions that set ENO = 0: SM1.1 (overflow), SM4.
SIMATIC Instructions Multiply Integer and Divide Integer L A D MUL_I EN ENO F B D IN1 OUT OUT The Multiply Integer instruction multiplies two 16-bit integers and produces a 16-bit product. The Divide Integer instruction divides two 16-bit integers and produces a 16-bit quotient. No remainder is kept. The overflow bit is set if the result is greater than a word output.
SIMATIC Instructions Multiply Double Integer and Divide Double Integer L A D MUL_DI EN ENO F B D IN1 OUT OUT IN2 DIV_DI EN ENO IN1 OUT OUT IN2 S T L 3 221 The Multiply Double Integer instruction multiplies two 32-bit integers and produces a 32-bit product. The Divide Double Integer instruction divides two 32-bit integers and produces a 32-bit quotient. No remainder is kept. In LAD and FBD: IN1
SIMATIC Instructions Multiply Integer To Double Integer and Divide Integer to Double Integer L A D MUL ENO EN F B D IN1 OUT OUT IN2 DIV EN The Divide Integer to Double Integer instruction divides two 16-bit integers and produces a 32-bit result consisting of a 16-bit remainder (most-significant) and a 16-bit quotient (least-significant). ENO IN1 OUT OUT In the STL Multiply instruction, the least-significant word (16 bits) of the 32-bit OUT is used as one of the factors.
SIMATIC Instructions Math Examples LAD STL Network 1 I0.0 EN ADD_I ENO AC1 IN1 OUT OUT AC0 IN2 EN AC0 MUL ENO IN1 OUT OUT AC1 VW102 VD100 IN2 EN DIV ENO OUT VW202 IN1 OUT VW10 NETWORK 1 LD I0.0 +I AC1, AC0 MUL AC1, VD100 DIV VW10, VD200 VD200 IN2 FBD Network 1 I0.
SIMATIC Instructions Increment Byte and Decrement Byte L A D F B D INC_B EN ENO The Increment Byte and Decrement Byte instructions add or subtract 1 to or from the input byte (IN) and place the result into the variable specified by OUT. IN Increment and decrement byte operations are unsigned.
SIMATIC Instructions Increment Double Word and Decrement Double Word L A D INC_DW ENO EN F B D IN S T L OUT The Increment Double Word and Decrement Double Word instructions add or subtract 1 to or from the input double word (IN) and place the result in OUT. In LAD and FBD: IN + 1 = OUT IN - 1 = OUT DEC_DW EN ENO Increment and decrement double word operations are signed (16#7FFFFFFF > 16#80000000).
SIMATIC Instructions Increment, Decrement Example LAD I4.0 STL INC_W EN ENO AC0 IN OUT LD INCW DECD I4.0 AC0 VD100 AC0 DEC_DW EN ENO VD100 IN OUT VD100 FBD I4.
SIMATIC Instructions 9.9 SIMATIC Real Math Instructions Add Real, Subtract Real L A D EN F B D ADD_R ENO IN1 OUT OUT The Add Real and Subtract Real instructions add or subtract two 32-bit real numbers and produce a 32-bit real number result (OUT). In LAD and FBD: IN1 + IN2 = OUT IN1 - IN2 = OUT In STL: IN1 + OUT = OUT OUT - IN1 = OUT IN2 SUB_R EN ENO IN1 OUT OUT IN2 S T L Error conditions that set ENO = 0: SM1.1 (overflow), SM4.
SIMATIC Instructions Multiply Real, Divide Real L A D MUL_R EN ENO F B D IN1 OUT OUT IN2 The Multiply Real instruction multiplies two 32-bit real numbers, and produces a 32-bit real number result (OUT). The Divide Real instruction divides two 32-bit real numbers, and produces a 32-bit real number quotient. In LAD and FBD: IN1
SIMATIC Instructions Math Examples LAD Network 1 I0.0 EN STL NETWORK 1 LD I0.0 +R AC1, AC0 *R AC1, VD100 /R VD10, VD200 ADD_R ENO AC1 IN1 OUT OUT AC0 IN2 AC0 MUL_R EN ENO AC1 VD100 IN1 OUT OUT VD100 IN2 DIV_R EN ENO VD100 VD10 OUT IN1 OUT VD200 IN2 FBD Network 1 I0.0 EN MUL_R EN ENO ADD_R ENO AC1 IN1 OUT OUT AC0 IN2 AC0 AC1 VD100 DIV_R EN ENO IN1 OUT OUT VD100 VD100 VD10 IN2 IN1 OUT OUT VD200 IN2 Application Add AC1 4000.0 Multiply AC1 400.00 plus AC0 6000.
SIMATIC Instructions PID Loop L A D PID EN ENO F B D TBL LOOP The PID Loop instruction executes a PID loop calculation on the referenced LOOP based on the input and configuration information in Table (TBL). Error conditions that set ENO = 0: SM1.1 (overflow), SM4.3 (run-time), 0006 (indirect address) This instruction affects the following Special Memory bits: SM1.
SIMATIC Instructions PID Algorithm In steady state operation, a PID controller regulates the value of the output so as to drive the error (e) to zero. A measure of the error is given by the difference between the setpoint (SP) (the desired operating point) and the process variable (PV) (the actual operating point).
SIMATIC Instructions Since the digital computer must calculate the output value each time the error is sampled beginning with the first sample, it is only necessary to store the previous value of the error and the previous value of the integral term. As a result of the repetitive nature of the digital computer solution, a simplification in the equation that must be solved at any sample time can be made.
SIMATIC Instructions Proportional Term The proportional term MP is the product of the gain (KC), which controls the sensitivity of the output calculation, and the error (e), which is the difference between the setpoint (SP) and the process variable (PV) at a given sample time.
SIMATIC Instructions Differential Term The differential term MD is proportional to the change in the error. The equation for the differential term: MDn = KC * TD / TS * ((SPn - PVn) - (SPn - 1 - PVn - 1)) To avoid step changes or bumps in the output due to derivative action on setpoint changes, this equation is modified to assume that the setpoint is a constant (SPn = SPn - 1).
SIMATIC Instructions Converting and Normalizing the Loop Inputs A loop has two input variables, the setpoint and the process variable. The setpoint is generally a fixed value such as the speed setting on the cruise control in your automobile. The process variable is a value that is related to loop output and therefore measures the effect that the loop output has on the controlled system.
SIMATIC Instructions Converting the Loop Output to a Scaled Integer Value The loop output is the control variable, such as the throttle setting in the example of the cruise control on the automobile. The loop output is a normalized, real number value between 0.0 and 1.0. Before the loop output can be used to drive an analog output, the loop output must be converted to a 16-bit, scaled integer value. This process is the reverse of converting the PV and SP to a normalized value.
SIMATIC Instructions Variables and Ranges The process variable and setpoint are inputs to the PID calculation. Therefore the loop table fields for these variables are read but not altered by the PID instruction. The output value is generated by the PID calculation, so the output value field in the loop table is updated at the completion of each PID calculation. The output value is clamped between 0.0 and 1.0.
SIMATIC Instructions Modes There is no built-in mode control for S7-200 PID loops. The PID calculation is performed only when power flows to the PID box. Therefore, “automatic” or “auto” mode exists when the PID calculation is performed cyclically. “Manual” mode exists when the PID calculation is not performed. The PID instruction has a power-flow history bit, similar to a counter instruction.
SIMATIC Instructions Error Conditions When it is time to compile, the CPU will generate a compile error (range error) and the compilation will fail if the loop table start address or PID loop number operands specified in the instruction are out of range. Certain loop table input values are not range checked by the PID instruction. You must take care to ensure that the process variable and setpoint (as well as the bias and previous process variable if used as inputs) are real numbers between 0.0 and 1.0.
SIMATIC Instructions PID Program Example In this example, a water tank is used to maintain a constant water pressure. Water is continuously being taken from the water tank at a varying rate. A variable speed pump is used to add water to the tank at a rate that will maintain adequate water pressure and also keep the tank from being emptied. The setpoint for this system is a water level setting that is equivalent to the tank being 75% full.
SIMATIC Instructions LAD STL MAIN OB1 Network 1 SM0.1 Network 1 LD SM0.1 CALL 0 SBR0 EN //On the first scan call //the initialization //subroutine. SUBROUTINE 0 Network 1 EN MOV_R ENO 0.75 IN OUT SM0.0 VD104 MOV_R EN ENO 0.25 IN OUT VD112 MOV_R EN ENO 0.10 IN OUT EN MOV_R ENO 30.0 IN OUT VD116 VD120 Network 1 LD SM0.0 MOVR 0.75, VD104 //Load the loop setpoint. // = 75% full. MOVR 0.25, VD112 //Load the loop gain=0.25. MOVR 0.10, VD116 //Load the loop sample //time = 0.1 seconds.
SIMATIC Instructions LAD INTERRUPT 0 Network 1 SM0.0 I_DI EN ENO AIW0 IN OUT STL NETWORK 1 AC0 DI_R EN ENO AC0 IN OUT AC0 DIV_R EN ENO AC0 IN1 32000 IN2 OUT //Convert PV to a //normalized real //number value - PV is //a unipolar input and //cannot be negative. AC0 LD SM0.0 ITD AIW0, AC0 //Save the unipolar //analog value in //the accumulator. DTR AC0, AC0 //Convert the 32-bit //integer to a real //number. /R 32000.0, AC0 //Normalize the value //in the //accumulator.
SIMATIC Instructions FBD MAIN OB1 Network 1 SBR0 SM0.1 EN SUBROUTINE 0 SM0.0 0.75 MOV_R EN ENO IN OUT MOV_R EN ENO 0.25 IN VD104 MOV_R EN ENO IN 30.0 0 10 OUT OUT MOV_R EN ENO VD112 MOV_R EN ENO VD120 0.0 IN ATCH EN ENO INT OUT 0.10 IN OUT VD116 MOV_B EN ENO VD124 100 IN OUT SMB34 ENI EVNT INTERRUPT 0 Network 1 I_DI SM0.0 EN ENO AIW0 IN OUT DI_R EN ENO AC0 AC0 IN OUT DIV_R EN ENO OUT AC0 AC0 IN1 OUT MOV_R EN ENO AC0 AC0 IN OUT VD100 32000 IN2 Network 2 I0.
SIMATIC Instructions Square Root L A D L A D F B D S T L SQRT EN ENO The Square Root instruction takes the square root of a 32-bit real number (IN) and produces a 32-bit real number result (OUT) as shown in the equation: IN √ IN = OUT SQRT 3 221 3 222 OUT IN, OUT 3 Error conditions that set ENO = 0: SM1.1 (overflow), SM4.3 (run-time), 0006 (indirect address) This instruction affects the following Special Memory bits: SM1.0 (zero); SM1.1 (overflow); SM1.2 (negative). 224 SM1.
SIMATIC Instructions 9.10 SIMATIC Move Instructions Move Byte, Move Word, Move Double Word, Move Real L A D The Move Byte instruction moves the input byte (IN) to the output byte (OUT). The input byte is not altered by the move. MOV_B EN ENO F B D IN OUT The Move Word instruction moves the input word (IN) to the output word (OUT). The input word is not altered by the move. MOV_W EN ENO IN The Move Double Word instruction moves the input double word (IN) to the output double word (OUT).
SIMATIC Instructions Block Move Byte, Block Move Word, Block Move Double Word L A D BLKMOV_B EN ENO F B D IN The Block Move Byte instruction moves the number of bytes (N) from the input address IN to the output address OUT. N has a range of 1 to 255. The Block Move Word instruction moves the number of words (N), from the input address IN to the output address OUT. N has a range of 1 to 255.
SIMATIC Instructions Block Move Example LAD STL Move Array 1 (VB20 to VB23) to Array 2 (VB100 to VB103) BLKMOV_B EN ENO I2.1 VB20 4 IN OUT LD BMB I2.1 VB20, VB100, 4 VB100 N FBD BLKMOV_B I2.
SIMATIC Instructions Swap Bytes L A D The Swap Bytes instruction exchanges the most significant byte with the least significant byte of the word (IN). SWAP EN ENO F B D IN S T L SWAP Error conditions that set ENO = 0: SM4.3 (run-time), 0006 (indirect address) IN 3 3 3 221 222 224 Inputs/Outputs IN Operands Data Types VW, IW, QW, MW, SW, SMW, LW, T, C, AC, *VD, *AC, *LD WORD Move and Swap Examples LAD STL LD MOVB SWAP MOV_B EN ENO I2.1 VB50 AC0 IN OUT EN SWAP ENO I2.
SIMATIC Instructions Memory Fill L A D FILL_N EN ENO F B D IN The Memory Fill instruction fills memory starting at the output word (OUT), with the word input pattern (IN) for the number of words specified by N. N has a range of 1 to 255. OUT Error conditions that set ENO = 0: SM4.
SIMATIC Instructions 9.11 SIMATIC Table Instructions Add to Table L A D AD_T_TBL EN ENO F B D DATA TBL S T L ATT DATA, TABLE 3 3 3 221 222 224 The Add To Table instruction adds word values (DATA) to the table (TBL). The first value of the table is the maximum table length (TL). The second value is the entry count (EC), which specifies the number of entries in the table. (See Figure 9-32.) New data are added to the table after the last entry.
SIMATIC Instructions Add to Table Example LAD STL LD ATT AD_T_TBL EN ENO I3.0 VW100 DATA VW200 TBL I3.0 VW100, VW200 FBD I3.0 AD_T_TBL EN ENO VW100 DATA VW200 TBL Application Before execution of ATT VW100 1234 VW200 VW202 VW204 VW206 VW208 VW210 VW212 VW214 0006 0002 5431 8942 xxxx xxxx xxxx xxxx Figure 9-32 TL (max. no.
SIMATIC Instructions Table Find L A D TBL_FIND EN ENO F B D SRC PTN INDX CMD S T L FND= SRC, PATRN INDX FND<> SRC, PATRN, INDX FND< SRC, PATRN, INDX FND> SRC, PATRN, INDX 3 3 3 221 222 224 Inputs/Outputs The Table Find instruction searches the table (SRC), starting with the table entry specified by INDX, for the data value (PTN) that matches the search criteria defined by CMD. The command parameter (CMD) is given a numeric value of 1 to 4 that corresponds to =, <>, <, and >, respectively.
SIMATIC Instructions Table Find Example LAD STL LD FND= I2.1 TBL_FIND EN ENO VW202 16#3130 SRC PTN AC1 1 I2.1 VW202, 16#3130, AC1 FBD When I2.1 is on, search the table for a value equal to 3130 HEX. I2.1 VW202 INDX 16#3130 CMD AC1 1 TBL_FIND EN ENO SRC PTN INDX CMD Application This is the table you are searching. If the table was created using ATT, LIFO, and FIFO instructions, VW200 contains the maximum number of allowed entries and is not required by the Find instructions.
SIMATIC Instructions First-In-First-Out L A D The First-In-First-Out instruction removes the first entry in the table (TBL), and outputs the value to a specified location (DATA). All other entries of the table are shifted up one location. The entry count in the table is decremented for each instruction execution. FIFO ENO OUT TBL DATA EN F B D S T L Error conditions that set ENO = 0: SM1.5 (empty table), SM4.
SIMATIC Instructions Last-In-First-Out L A D LIFO EN ENO F B D OUT DATA TBL The Last-In-First-Out instruction removes the last entry in the table (TBL), and outputs the value to a location specified by DATA. The entry count in the table is decremented for each instruction execution. Error conditions that set ENO = 0: SM1.5 (empty table), SM4.
SIMATIC Instructions 9.12 SIMATIC Logical Operations Instructions And Byte, Or Byte, Exclusive Or Byte L A D WAND_B EN ENO F B D IN1 OUT IN2 WOR_B EN ENO IN1 OUT The And Byte instruction ANDs the corresponding bits of two input bytes and loads the result (OUT) in a byte. The Or Byte instruction ORs the corresponding bits of two input bytes and loads the result (OUT) in a byte. The Exclusive Or Byte instruction XORs the corresponding bits of two input bytes and loads the result (OUT) in a byte.
SIMATIC Instructions And Word, Or Word, Exclusive Or Word L A D WAND_W EN ENO F B D IN1 OUT IN2 WOR_W EN ENO IN1 OUT The And Word instruction ANDs the corresponding bits of two input words and loads the result (OUT) in a word. The Or Word instruction ORs the corresponding bits of two input words and loads the result (OUT) in a word. The Exclusive Or Word instruction XORs the corresponding bits of two input words and loads the result (OUT) in a word. IN2 Error conditions that set ENO = 0: SM4.
SIMATIC Instructions And Double Word, Or Double Word, Exclusive Or Double Word L A D WAND_DW EN ENO F B D IN1 OUT IN2 WOR_DW EN ENO IN1 OUT The And Double Word instruction ANDs the corresponding bits of two double word inputs and loads the result (OUT) in a double word. The Or Double Word instruction ORs the corresponding bits of two double word inputs and loads the result (OUT) in a double word.
SIMATIC Instructions And, Or, and Exclusive Or Instructions Example LAD I4.0 STL WAND_W EN ENO AC1 IN1 AC0 IN2 OUT LD ANDW ORW XORW AC0 I4.0 AC1, AC0 AC1, VW100 AC1, AC0 WOR_W EN ENO AC1 IN1 VW100 IN2 OUT VW100 WXOR_W EN ENO AC1 IN1 AC0 IN2 OUT AC0 FBD I4.
SIMATIC Instructions Invert Byte, Invert Word, Invert Double Word Instructions L A D INV_B EN ENO F B D IN OUT INV_W EN ENO IN OUT INV_DW EN ENO IN Double Word 9-114 INVB OUT INVW OUT INVD OUT 3 3 3 221 222 224 Inputs/Outputs The Invert Double Word instruction forms the ones complement of the input double word IN, and loads the result in double word value OUT. Error conditions that set ENO = 0: SM4.
SIMATIC Instructions Invert Example LAD STL I4.0 EN INV_W ENO LD INVW I4.0 AC0 FBD AC0 IN OUT AC0 I4.
SIMATIC Instructions 9.13 SIMATIC Shift and Rotate Instructions Shift Right Byte, Shift Left Byte L A D SHR_B EN ENO F B D IN OUT OUT N SHL_B EN ENO IN OUT OUT N The Shift instructions fill with zeros as each bit is shifted out. If the shift count (N) is greater than or equal to 8, the value is shifted a maximum of 8 times. If the shift count is greater than 0, the overflow memory bit (SM1.1) takes on the value of the last bit shifted out. The zero memory bit (SM1.
SIMATIC Instructions Shift Right Word, Shift Left Word L A D SHR_W EN ENO F B D IN OUT OUT N SHL_W EN ENO IN OUT OUT N S T L The Shift Right Word and Shift Left Word instructions shift the input word (IN) value right or left by the shift count (N), and load the result in the output word (OUT). The Shift instructions fill with zeros as each bit is shifted out. If the shift count (N) is greater than or equal to 16, the value is shifted a maximum of 16 times.
SIMATIC Instructions Shift Right Double Word, Shift Left Double Word L A D SHR_DW EN ENO F B D IN OUT OUT N SHL_DW EN ENO IN OUT OUT N The Shift instructions fill with zeros as each bit is shifted out. If the shift count (N) is greater than or equal to 32, the value is shifted a maximum of 32 times. If the shift count is greater than 0, the overflow memory bit (SM1.1) takes on the value of the last bit shifted out. The zero memory bit (SM1.0) is set if the result of the shift operation is zero.
SIMATIC Instructions Rotate Right Byte, Rotate Left Byte L A D ROR_B EN ENO F B D IN OUT OUT N ROL_B EN ENO IN OUT OUT N S T L RRB OUT, N RLB OUT, N 3 3 3 221 222 224 The Rotate Right Byte and Rotate Left Byte instructions rotate the input byte value (IN) right or left by the shift count (N), and load the result in the output byte (OUT). If the shift count (N) is greater than or equal to 8, a modulo-8 operation is performed on the shift count (N) before the rotation is executed.
SIMATIC Instructions Rotate Right Word, Rotate Left Word L A D ROR_W ENO EN F B D IN OUT OUT N EN ROL_W ENO IN OUT OUT N S T L RRW OUT, N RLW OUT, N 3 3 3 221 222 224 The Rotate Right Word and Rotate Left Word instructions rotate the input word value (IN) right or left by the shift count (N), and load the result in the output word (OUT). If the shift count (N) is greater than or equal to 16, a modulo-16 operation is performed on the shift count (N) before the rotation is executed.
SIMATIC Instructions Rotate Right Double Word, Rotate Left Double Word L A D ROR_DW ENO EN F B D IN OUT OUT N ROL_DW EN ENO IN OUT OUT N S T L RRD OUT, N RLD OUT, N 3 3 3 221 222 224 The Rotate Right Double Word and Rotate Left Double Word instructions rotate the input double word value (IN) right or left by the shift count (N), and load the result in the output double word (OUT).
SIMATIC Instructions Shift and Rotate Examples LAD I4.0 STL LD RRW SLW ROR_W EN ENO AC0 IN 2 N VW200 FBD OUT SHL_W EN ENO IN OUT AC0 I4.0 AC0 ROR_W EN ENO IN OUT AC0 VW200 SHL_W EN ENO IN OUT VW200 VW200 2 3 I4.0 AC0, 2 VW200, 3 N N 3 N Application Rotate Before rotate AC0 0100 0000 0000 0001 After first rotate AC0 1010 0000 0000 0000 After second rotate AC0 0101 0000 0000 0000 Zero Memory Bit (SM1.0) Overflow Memory Bit (SM1.
SIMATIC Instructions Shift Register Bit L A D SHRB EN ENO F B D DATA S_BIT N S T L SHRB DATA, S_BIT, N 3 3 3 221 222 224 The Shift Register Bit (SHRB) instruction shifts the value of DATA into the Shift Register. S_BIT specifies the least significant bit of the Shift Register. N specifies the length of the Shift Register and the direction of the shift (Shift Plus = N, Shift Minus = -N). Each bit shifted out by the SHRB instruction is placed in the overflow memory bit (SM1.1).
SIMATIC Instructions Understanding the Shift Register Bit Instruction The Shift Register Bit instruction provides an easy method for sequencing and controlling product flow or data. Use the Shift Register Bit instruction to shift the entire register one bit, once per scan. The Shift Register Bit instruction is defined by both the least significant bit (S_BIT) and the number of bits specified by the length (N). Figure 9-41 shows an example of the Shift Register Bit instruction.
SIMATIC Instructions Shift Register Bit Example LAD I0.2 STL P SHRB EN ENO I0.3 DATA V100.0 4 LD EU SHRB I0.2 I0.3, V100.0, 4 S_BIT N FBD I0.2 IN P SHRB EN ENO OUT I0.3 V100.0 4 DATA S_BIT N Timing Diagram I0.2 Positive transition (P) I0.3 First shift Second shift MSB 7 Before first shift V100 LSB 0 0 1 0 1 S_BIT I0.3 1 1 S_BIT I0.3 1 0 S_BIT I0.3 Overflow (SM1.1) x After first shift V100 1 0 Overflow (SM1.1) 0 After second shift V100 0 1 Overflow (SM1.
SIMATIC Instructions 9.14 SIMATIC Conversion Instructions BCD to Integer, Integer to BCD L A D BCD_I EN ENO F B D IN OUT I_BCD EN ENO IN S T L OUT BCDI OUT IBCD OUT 3 3 3 221 222 224 Inputs/Outputs The BCD to Integer instruction converts the input Binary-Coded Decimal (IN) to an integer value and loads the result into the variable specified by OUT. The valid range for IN is 0 to 9999 BCD.
SIMATIC Instructions Round L A D ROUND EN ENO F B D IN OUT The Round instruction converts the real value (IN) to a double integer value and places the result into the variable specified by OUT. If the fraction portion is 0.5 or greater, the number is rounded up. Error conditions that set ENO = 0: SM1.1 (overflow), SM4.3 (run-time), 0006 (indirect address) S T L ROUND IN, OUT 3 3 3 221 222 224 These instructions affect the following Special Memory bits: SM1.
SIMATIC Instructions Double Integer to Integer L A D DI_I EN ENO F B D IN S T L DTI OUT IN, OUT 3 3 3 221 222 224 Inputs/Outputs The Double Integer to Integer instruction converts the double integer value (IN) to an integer value and places the result into the variable specified by OUT. If the value that you are converting is too large to be represented in the output, then the overflow bit is set and the output is not affected. Error conditions that set ENO = 0: SM1.1 (overflow), SM4.
SIMATIC Instructions Byte to Integer L A D B_I EN ENO F B D IN OUT The Byte to Integer instruction converts the byte value (IN) to an integer value and places the result into the variable specified by OUT. The byte is unsigned, therefore there is no sign extension. Error conditions that set ENO = 0: SM4.
SIMATIC Instructions Convert Example LAD Network 1 I0.0 I_DI EN ENO C10 IN OUT DI_R EN ENO STL Clear accumulator 1. Load counter value (number of inches) into AC1. AC1 Network 1 LD I0.0 ITD C10, DTR AC1, MOVR VD0, *R VD4, ROUND VD8, AC1 VD0 VD8 VD8 VD12 Convert to a real number. AC1 IN OUT VD0 VD0 MUL_R EN ENO IN1 OUT VD8 VD4 Multiply by 2.54 to change to centimeters. IN2 ROUND EN ENO Convert back to an integer. VD8 Network 2 I3.0 AC0 IN OUT VD12 Network 2 LD I3.
SIMATIC Instructions Decode L A D DECO EN ENO F B D IN OUT The Decode instruction sets the bit in the output word (OUT) that corresponds to the bit number represented by the least significant “nibble” (4 bits) of the input byte (IN). All other bits of the output word are set to 0. Error conditions that set ENO = 0: SM4.
SIMATIC Instructions Decode, Encode Examples LAD I3.1 DECO EN ENO STL LD DECO Set the bit that corresponds to the error code in AC2. I3.1 AC2, VW40 FBD AC2 IN OUT VW40 I3.1 DECO EN ENO AC2 IN OUT VW40 Application AC2 contains the error code 3. The DECO instruction sets the bit in VW40 that corresponds to this error code. 3 AC2 DECO 15 3 0 VW40 0000 0000 0000 1000 Figure 9-43 Example of Setting an Error Bit Using Decode LAD I3.1 ENCO EN ENO AC2 IN OUT STL LD ENCO I3.
SIMATIC Instructions Segment L A D F B D S T L EN SEG ENO IN OUT SEG The Segment instruction uses the character specified by IN to generate a bit pattern (OUT) that illuminates the segments of a seven-segment display. The illuminated segments represent the character in the least significant digit of the input byte (IN). IN, OUT 3 3 3 221 222 224 Error conditions that set ENO = 0: SM4.
SIMATIC Instructions Segment Example LAD STL LD SEG I3.3 VB48 EN SEG ENO IN OUT I3.3 VB48, AC1 FBD AC1 I3.
SIMATIC Instructions ASCII to HEX, HEX to ASCII L A D The ASCII to HEX instruction converts the ASCII string of length (LEN), starting at IN, to hexadecimal digits starting at OUT. The maximum length of the ASCII string is 255 characters. ATH ENO EN F B D IN OUT The HEX to ASCII instruction converts the hexadecimal digits, starting with the input byte (IN), to an ASCII string starting at OUT. The number of hexadecimal digits to be converted is specified by length (LEN).
SIMATIC Instructions Integer to ASCII L A D ITA ENO EN F B D IN OUT FMT S T L Inputs/Outputs ITA IN, OUT, FMT 3 3 3 221 222 224 The Integer to ASCII instruction converts an integer word (IN) to an ASCII string. The format (FMT) specifies the conversion precision to the right of the decimal, and whether the decimal point is to be shown as a comma or a period. The resulting conversion is placed in 8 consecutive bytes beginning with OUT. The ASCII string is always 8 characters.
SIMATIC Instructions The format operand (FMT) for the ITA (Integer to ASCII) instruction is defined in Figure 9-48. The size of the output buffer is always 8 bytes. The number of digits to the right of the decimal point in the output buffer is specified by the nnn field. The valid range of the nnn field is 0 to 5. Specifying 0 digits to the right of the decimal point causes the value to be displayed without a decimal point. For values of nnn bigger than 5, the output buffer is filled with ASCII spaces.
SIMATIC Instructions Double Integer to ASCII L A D DTA ENO EN F B D IN OUT FMT S T L Inputs/Outputs The Double Integer to ASCII instruction converts a double word (IN) to an ASCII string. The format (FMT) specifies the conversion precision to the right of the decimal. The resulting conversion is placed in 12 consecutive bytes beginning with OUT. Error conditions that set ENO = 0: SM4.
SIMATIC Instructions Figure 9-49 gives examples of values that are formatted using a decimal point (c = 0) with four digits to the right of the decimal point (nnn = 100). MSB FMT 7 0 Example: LSB 6 0 5 0 4 0 3 2 c n 1 n 0 n c = comma (1) or decimal point (0) nnn = digits to right of decimal point Out Out Out Out Out Out Out Out Out Out Out Out +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 . 0 0 1 2 in=-12 - 0 6 7 1 2 3 .
SIMATIC Instructions The format operand (FMT) for the RTA instruction is defined in Figure 9-50. The size of the output buffer is specified by the ssss field. A size of 0, 1, or 2 bytes is not valid. The number of digits to the right of the decimal point in the output buffer is specified by the nnn field. The valid range of the nnn field is 0 to 5. Specifying 0 digits to the right of the decimal point causes the value to be displayed without a decimal point.
SIMATIC Instructions 9.15 SIMATIC Program Control Instructions End L A D END The Conditional END instruction terminates the main user program based upon the condition of the preceding logic. Operands: F B D END S T L None Data Types: None END 3 3 3 221 222 224 Note You can use the Conditional END instruction in the main program, but you cannot use it in either subroutines or interrupt routines. Note Micro/WIN 32 automatically adds an unconditional end to the main user program.
SIMATIC Instructions Watchdog Reset L A D WDR The Watchdog Reset instruction allows the CPU system watchdog timer to be retriggered. This extends the time that the scan is allowed to take without getting a watchdog error. Operands: F B D None WDR S T L WDR 3 3 3 221 222 224 Considerations for Using the WDR Instruction to Reset the Watchdog Timer You should use the Watchdog Reset instruction carefully.
SIMATIC Instructions Stop, End, and WDR Example LAD Network 1 SM5.0 STL STOP When an I/O error is detected, force the transition to STOP mode. WDR When M5.6 is on, retrigger the Watchdog Reset (WDR) to allow the scan time to be extended. . . . Network 15 M5.6 . . . Network 78 I0.0 END . . . Network 1 LD SM5.0 STOP . . . Network 15 LD M5.6 WDR . . . Network 78 LD I0.0 END When I0.0 is on, terminate the main program. FBD Network 1 STOP SM5.
SIMATIC Instructions Jump to Label, Label L A D The Jump to Label instruction performs a branch to the specified label (n) within the program. When a jump is taken, the top of stack value is always a logical 1. n JMP n LBL F B D The Label instruction marks the location of the jump destination (n). Operands: n JMP JMP n LBL n 3 3 3 221 222 224 0 to 255 Data Types: WORD Both the Jump and corresponding Label must be in the main program, a subroutine, or an interrupt routine.
SIMATIC Instructions Subroutine, Return from Subroutine L A D SBR RET F B D L A D EN SBRn The Call Subroutine instruction transfers control to the subroutine (n). You can use a Call Subroutine instruction with or without parameters. To add a subroutine, select Edit > Insert > Subroutine from the menu. The Conditional Return from Subroutine instruction is used to terminate a subroutine based upon the preceding logic.
SIMATIC Instructions Calling a Subroutine With Parameters Subroutines may contain passed parameters. The parameters are defined in the local variable table of the subroutine (Figure 9-53). The parameters must have a symbol name (maximum of 8 characters), a variable type, and a data type. Sixteen parameters can be passed to or from a subroutine.
SIMATIC Instructions The data type field in the local variable table defines the size and format of the parameter. The parameter types are: Power Flow: Boolean power flow is allowed only for bit (Boolean) inputs. This declaration tells STEP 7-Micro/WIN 32 that this input parameter is the result of power flow based on a combination of bit logic instructions. Boolean power flow inputs must appear first in the local variable table before any other type input.
SIMATIC Instructions The data element size and type are represented in the coding of the parameters. Assignment of parameter values to local memory in the subroutine is as follows: Parameter values are assigned to local memory in the order specified by the call subroutine instruction with parameters starting at L.0. One to eight consecutive bit parameter values are assigned to a single byte starting with Lx.0 and continuing to Lx.7.
SIMATIC Instructions Subroutine, and Return from Subroutine Example LAD STL MAIN Network 1 SM0.1 SBR10 EN On the first scan: Call SBR10 for initialization. . . SUBROUTINE 10 . . . . Network 6 M14.3 Start of Subroutine 10 RET . . . A conditional return (RET) from Subroutine 10 may be used. Each subroutine is automatically terminated by STEP 7 Micro/WIN 32 3.0. This terminates Subroutine 10. Network 1 LD SM0.1 CALL 10 . . . . Network 6 LD M14.3 CRET . . . FBD MAIN SM0.
SIMATIC Instructions For, Next L A D FOR ENO EN INDX The NEXT instruction marks the end of the FOR loop, and sets the top of the stack to 1. INIT FINAL NEXT F B D FOR EN ENO INDX INIT FINAL NEXT S T L FOR The FOR instruction executes the instructions between the FOR and the NEXT. You must specify the index value or current loop count (INDX), the starting value (INIT), and the ending value (FINAL).
SIMATIC Instructions Here are some guidelines for using the FOR/NEXT loop: If you enable the FOR/NEXT loop, it continues the looping process until it finishes the iterations, unless you change the final value from within the loop itself. You can change the values while the FOR/NEXT is in the looping process. When the loop is enabled again, it copies the initial value into the index value (current loop number). The FOR/NEXT instruction resets itself the next time it is enabled.
SIMATIC Instructions For/Next Example LAD Network 1 I2.0 STL When I2.0 comes on, the outside loop indicated by arrow 1 is executed 100 times. FOR VW100 EN INDX 1 INIT 100 Network 10 I2.1 VW225 ENO The inside loop indicated by arrow 2 is executed twice for each execution of the outside loop when I2.1 is on. FINAL FOR EN ENO INDX 1 INIT 2 FINAL 1 Network LD I2.0 FOR VW100, 1, 100 . . . Network LD I2.1 FOR VW225, 1, 2 . . . 2 Network 15 Network NEXT . .
SIMATIC Instructions Sequence Control Relay L A D S bit SCR S bit SCRT SCRE F B D S bit SCR The Load Sequence Control Relay instruction marks the beginning of an SCR segment. When the S bit is on, power flow is enabled to the SCR segment. The SCR segment must be terminated with an SCRE instruction. The Sequence Control Relay Transition instruction identifies the SCR bit to be enabled (the next S bit to be set).
SIMATIC Instructions LSCR Load the value of Sx.y onto the SCR and logic stacks. BEFORE AFTER S stack initial value of S Figure 9-57 ivs Logic stack iv0 S stack S bit Sx.y Logic stack Sx.
SIMATIC Instructions SCR Example Figure 9-58 shows an example of the operation of SCRs. In this example, the first scan bit SM0.1 is used to set S0.1, which will be the active State 1 on the first scan. After a 2-second delay, T37 causes a transition to State 2. This transition deactivates the State 1 SCR (S0.1) segment and activates the State 2 SCR (S0.2) segment. LAD Network 1 SM0.1 Network 2 S0.1 S 1 S0.1 SCR Network 3 SM0.0 Q0.4 S 1 Q0.
SIMATIC Instructions LAD STL S0.2 SCR Network 6 Network 7 SM0.0 Q0.2 S 1 IN 250 Network 8 T38 Turn on the green light on Third Street. T38 TON Network 7 LD SM0.0 S Q0.2, 1 TON T38, 250 Start a 25-second timer. PT S0.3 SCRT Transition to State 3 after a 25-second delay. Network 9 End of SCR region for State 2 SCRE . . . FBD Network 1 Network 6 LSCR S0.2 Beginning of State 2 control region Network 8 LD T38 SCRT S0.3 Network 9 SCRE . . . S0.1 SM0.
SIMATIC Instructions FBD Network 5 End of SCR region for State 1 SCRE Network 6 S0.2 SCRT SCR Beginning of State 2 control region Network 7 Q0.2 SM0.0 AND SM0.0 S EN 1 N IN 250 Turn on the green light on Third Street. T38 TON Start a 25-second timer. PT Network 8 T38 S0.3 SCRT SCRT Transition to State 3 after a 25-second delay.
SIMATIC Instructions The divergence of control streams can be implemented in an SCR program by using multiple SCRT instructions enabled by the same transition condition, as shown in Figure 9-60. LAD S3.4 SCR Network STL Beginning of State L control region Network ... Network LSCR S3.4 Network . . . Network M2.3 I2.1 S3.5 SCRT Transition to State M S6.5 SCRT Transition to State N SCRE End of SCR region for State L Network Network LD M2.3 A I2.1 SCRT S3.5 SCRT S6.
SIMATIC Instructions Convergence Control A similar situation arises when two or more streams of sequential states must be merged into a single stream. When multiple streams merge into a single stream, they are said to converge. When streams converge, all incoming streams must be complete before the next state is executed. Figure 9-61 depicts the convergence of two control streams.
SIMATIC Instructions The convergence of control streams can be implemented in an SCR program by making the transition from state L to state L’ and by making the transition from state M to state M’. When both SCR bits representing L’ and M’ are true, state N can the enabled as shown in Figure 9-62. LAD Network S3.4 SCR STL Beginning of State L control region. Network LSCR S3.4 Network . . . Network ... Network V100.5 S3.5 SCRT Transition to State L’. Network LD V100.5 SCRT S3.
SIMATIC Instructions FBD Network S3.4 SCR Beginning of State L control region. Network V100.5 S3.5 SCRT Transition to State L’. Network End of SCR region for State L. SCRE Network Network C50 S6.4 SCR Beginning of State M control region. S6.5 SCRT Transition to State M’. Network SCRE End of SCR region for State M. Network S5.0 AND EN S3.5 S6.5 1 S Enable State N. N S3.5 EN 1 R Reset State L’. N S6.5 EN 1 R Reset State M’.
SIMATIC Instructions In other situations, a control stream may be directed into one of several possible control streams, depending upon which transition condition comes true first. Such a situation is depicted in Figure 9-63. State L Transition Condition Transition Condition State M Figure 9-63 State N Divergence of Control Stream, Depending on Transition Condition An equivalent SCR program is shown in Figure 9-64. LAD Network S3.4 SCR STL Beginning of State L control region. Network Network .
SIMATIC Instructions FBD Network S3.4 SCR Beginning of State L control region. Network M2.3 S3.5 SCRT Transition to State M. Network I3.3 S6.5 SCRT Transition to State N. Network SCRE End of SCR region for State L.
SIMATIC Instructions ENO S T L AENO 3 221 3 3 222 224 ENO is a Boolean output for boxes in LAD and FBD. If a box has power flow at the EN input and is executed without error, the ENO output passes power flow to the next element. ENO can be used as an enable bit that indicates the successful completion of an instruction. The ENO bit is used with the top of stack to affect power flow for execution of subsequent instructions.
SIMATIC Instructions 9.16 SIMATIC Interrupt and Communications Instructions Attach Interrupt, Detach Interrupt L A D ATCH EN ENO F B D INT EVNT DTCH EN ENO The Attach Interrupt instruction associates an interrupt event (EVNT) with an interrupt routine number (INT), and enables the interrupt event. The Detach Interrupt instruction disassociates an interrupt event (EVNT) from all interrupt routines, and disables the interrupt event. Attach Interrupt: Error conditions that set ENO = 0: SM4.
SIMATIC Instructions Table 9-20 Interrupt Events Event Number 9-166 Interrupt Description CPU 221 CPU 222 CPU 224 0 Rising edge, I0.0 Y Y Y 1 Falling edge, I0.0 Y Y Y 2 Rising edge, I0.1 Y Y Y 3 Falling edge, I0.1 Y Y Y 4 Rising edge, I0.2 Y Y Y 5 Falling edge, I0.2 Y Y Y 6 Rising edge, I0.3 Y Y Y 7 Falling edge, I0.
SIMATIC Instructions Return from Interrupt L A D RETI The Conditional Return from Interrupt instruction may be used to return from an interrupt, based upon the condition of the preceding logic. To add an interrupt, select Edit Insert Interrupt from the menu. Operands: None Data Types: None F B D RETI S T L The Return from Interrupt routines are identified by separate program tabs in the STEP 7-Micro/WIN 32 screen.
SIMATIC Instructions Calling Subroutine From Interrupt Routines You can call one nesting level of subroutines from an interrupt routine. The accumulators and the logic stack are shared between an interrupt routine and a subroutine that is called. Sharing Data Between the Main Program and Interrupt Routines You can share data between the main program and one or more interrupt routines. For example, a part of your main program may provide data to be used by an interrupt routine, or vice versa.
SIMATIC Instructions Enable Interrupt, Disable Interrupt L A D ENI The Enable Interrupt instruction globally enables processing of all attached interrupt events. DISI The Disable Interrupt instruction globally disables processing of all interrupt events. Operands: F B D ENI DISI S T L ENI None Data Types: None When you make the transition to the RUN mode, interrupts are initially disabled. Once in RUN mode, you can enable all interrupts by executing the global Enable Interrupt instruction.
SIMATIC Instructions Table 9-21 Rising/Falling Edge Interrupts Supported I/O Interrupts S7-200 CPU I/O Points I0.0 to I0.3 The high-speed counter interrupts allow you to respond to conditions such as the current value reaching the preset value, a change in counting direction that might correspond to a reversal in the direction in which a shaft is turning, or an external reset of the counter.
SIMATIC Instructions Time-Based Interrupts Time-based interrupts include timed interrupts and the Timer T32/T96 interrupts. The CPU can support timed interrupts. You can specify actions to be taken on a cyclic basis using a timed interrupt. The cycle time is set in 1-ms increments from 1 ms to 255 ms. You must write the cycle time in SMB34 for timed interrupt 0, and in SMB35 for timed interrupt 1. The timed interrupt event transfers control to the appropriate interrupt routine each time the timer expires.
SIMATIC Instructions Understanding the Interrupt Priority and Queuing Interrupts are prioritized according to the fixed priority scheme shown below: Communication (highest priority) I/O interrupts Time-based interrupts (lowest priority) Interrupts are serviced by the CPU on a first-come-first-served basis within their respective priority assignments. Only one user-interrupt routine is ever being executed at any point in time.
SIMATIC Instructions Table 9-24 shows the interrupt event, priority, and assigned event number. Table 9-24 Interrupt Events in Priority Order Event Number Interrupt Description Priority Group Priority in Group 8 Port 0: Receive character 0 9 Port 0: Transmit complete 0 23 Port 0: Receive message complete 24 Port 1: Receive message complete 25 Port 1: Receive character 1 26 Port 1: Transmit complete 1 19 PTO 0 complete interrupt 0 20 PTO 1 complete interrupt 1 0 Rising edge, I0.
SIMATIC Instructions Interrupt Examples Figure 9-65 shows an example of the Interrupt Routine instructions. LAD STL MAIN OB1 Network 1 ATCH EN ENO SM0.1 4 INT 0 EVNT ENI Network 2 DTCH EN ENO SM5.0 0 EVNT Network 3 M5.0 DISI On the first scan: Define interrupt routine 4 to be a rising edge interrupt routine for I0.0. Network 1 LD SM0.1 ATCH 4, 0 ENI Globally enable interrupts. If an I/O error is detected, disable the rising edge interrupt for I0.0. (This rung is optional.
SIMATIC Instructions Figure 9-66 shows how to set up a timed interrupt to read the value of an analog input. LAD STL MAIN PROGRAM Network 1 SM0.1 First scan memory bit: Call Subroutine 0. SBR0 Network 1 LD SM0.1 CALL 0 SUBROUTINE 0 Network 1 SM0.0 Begin Subroutine 0. MOV_B EN ENO 100 IN OUT SMB34 ATCH EN ENO 0 10 Always on memory bit: Set timed interrupt 0 interval to 100 ms. Network 1 LD SM0.0 MOVB 100, SMB34 Global Interrupt Enable ATCH Attach timed interrupt 0 to Interrupt routine 0.
SIMATIC Instructions Network Read, Network Write L A D NETR EN ENO F B D TBL The Network Write instruction initiates a communication operation to write data to a remote device through the specified port (PORT), as defined by the table (TBL). PORT NETW EN ENO TBL PORT S T L The Network Read instruction initiates a communication operation to gather data from a remote device through the specified port (PORT), as defined by the table (TBL).
SIMATIC Instructions Byte Offset 0 D Done (function has been completed): A Active (function has been queued): E Error (function returned an error): 7 0 = not done 0 = not active 0 = no error 1 = done 1 = active 1 = error 0 D A E 0 Error code 1 Remote station address 2 Pointer to the data 3 area in the 4 remote station 5 (I, Q, M, or V) 6 Data length 7 Data byte 0 8 Data byte 1 22 Data byte 15 Remote station address: the address of the PLC whose data is to be accessed.
SIMATIC Instructions Example of Network Read and Network Write Figure 9-68 shows an example to illustrate the utility of the NETR and NETW instructions. For this example, consider a production line where tubs of butter are being filled and sent to one of four boxing machines (case packers). The case packer packs eight tubs of butter into a single cardboard box. A diverter machine controls the flow of butter tubs to each of the case packers.
SIMATIC Instructions The receive and transmit buffers for accessing the data in station 2 (located at VB200 and VB300, respectively) are shown in detail in Figure 9-69. The CPU 224 uses a NETR instruction to read the control and status information on a continuous basis from each of the case packers. Each time a case packer has packed 100 cases, the diverter notes this and sends a message to clear the status word using a NETW instruction.
SIMATIC Instructions LAD Network 1 SM0.1 Network 2 V200.7 VW20 8==I 100 2 MOV_B EN ENO IN OUT 0 68 FILL_N EN ENO IN OUT N MOV_B EN ENO 2 IN OUT MOV_D EN ENO &VB101 IN OUT STL SMB30 VW200 IN OUT IN OUT NETW EN ENO VB300 0 Network 3 V200.7 TBL PORT MOV_B EN ENO VB207 IN OUT / / MOV_B EN ENO / 2 IN OUT MOV_D EN ENO VB306 3 Reset the number of cases packed by case packer #1. When the Done bit is set, save the control data from VB400 case packer #1.
SIMATIC Instructions FBD Network 1 MOV_B EN ENO IN OUT SM0.1 2 FILL_N EN ENO 0 IN OUT 68 N SMB30 VW200 Network 2 AND ==I V200.7 SM0.0 VW208 100 2 MOV_B EN ENO 2 IN OUT MOV_B EN ENO IN OUT MOV_D EN ENO VB301 &VB101 IN OUT MOV_W EN ENO VB306 0 IN OUT VD302 NETW EN ENO VW307 VB300 Network 3 TBL 0 PORT V200.7 VB207 MOV_B EN ENO IN OUT VB400 Network 4 2 IN V200.6 V200.5 3 Figure 9-71 MOV_B EN ENO IN OUT MOV_D EN ENO MOV_B EN ENO AND SM0.
SIMATIC Instructions Transmit, Receive L A D XMT EN ENO F B D TBL The Transmit instruction invokes the transmission of the data buffer (TBL). The first entry in the data buffer specifies the number of bytes to be transmitted. PORT specifies the communication port to be used for transmission. PORT RCV EN ENO The XMT instruction is used in Freeport mode to transmit data by means of the communication port(s).
SIMATIC Instructions Understanding Freeport Mode You can select the Freeport mode to control the serial communication port of the CPU by means of the user program. When you select Freeport mode, the LAD program controls the operation of the communication port through the use of the receive interrupts, the transmit interrupts, the transmit instruction (XMT), and the receive instruction (RCV). The communication protocol is entirely controlled by the ladder program while in Freeport mode.
SIMATIC Instructions Freeport Initialization SMB30 and SMB130 configure the communication ports, 0 and 1, respectively, for Freeport operation and provide selection of baud rate, parity, and number of data bits. The Freeport control byte(s) description is shown in Table 9-25. Table 9-25 Special Memory Bytes SMB30 and SMB130 Port 0 Port 1 Format of SMB30 Format of SMB130 Description MSB 7 p LSB 0 p d b b b m m Freeport mode control byte SM30.6 and SM30.7 SM130.6 and SM130.
SIMATIC Instructions The XMT instruction can be used to generate a BREAK condition by setting the number of characters to zero and then executing the XMT instruction. This generates a BREAK condition on the line for 16-bit times at the current baud rate. Transmitting a BREAK is handled in the same manner as transmitting any other message, in that a XMT interrupt is generated when the BREAK is complete and SM4.5 or SM4.6 signal the current status of the XMT.
SIMATIC Instructions Table 9-26 Special Memory Bytes SMB86 to SMB94, and SMB186 to SMB194 Port 0 Port 1 SMB86 SMB186 Description MSB 7 n LSB 0 r e 0 0 t c p Receive message status byte n: 1 = Receive message terminated by user disable command r: 1 = Receive message terminated: error in input parameters or missing start or end condition e: 1 = End character received t: 1 = Receive message terminated: timer expired c: 1 = Receive message terminated: maximum character count achieved p 9-186
SIMATIC Instructions Table 9-26 Special Memory Bytes SMB86 to SMB94, and SMB186 to SMB194 Port 0 Port 1 SMB87 SMB187 Description MSB 7 n LSB 0 x y z m t 0 0 Receive message control byte n: 0 = Receive Message function is disabled. 1 = Receive Message function is enabled . The enable/disable receive message bit is checked each time the RCV instruction is executed. x: 0 = Ignore SMB88 or SMB188. 1 = Use the value of SMB88 or SMB188 to detect start of message. y; 0 = Ignore SMB89 or SMB189.
SIMATIC Instructions Table 9-26 Special Memory Bytes SMB86 to SMB94, and SMB186 to SMB194 Port 0 Port 1 Description SMB90 SMB91 SMB190 Idle line time period given in milliseconds. The first character received SMB191 after idle line time has expired is the start of a new message. SM90 (or SM190) is the most significant byte and SM91 (or SM191) is the least significant byte. SMB92 SMB93 SMB192 Inter-character/message timer time-out value given in milliseconds.
SIMATIC Instructions Receive and Transmit Example This sample program shows the use of Receive and Transmit. This program will receive a string of characters until a line feed character is received. The message is then transmitted back to the sender. LAD STL MAIN (OB1) Network 1 SM0.
SIMATIC Instructions INTERRUPT 0 Network 1 SMB86 MOV_B EN ENO ==B 16#20 10 IN OUT ATCH EN ENO 1 INT 10 EVNT RETI RCV EN ENO NOT VB100 0 Receive complete interrupt. SMB34 If receive status shows receive of end character, then attach a 10 ms timer to trigger a transmit, then return. Network LDB= MOVB ATCH CRETI NOT RCV 1 SMB86, 16#20 10, SMB34 2, 10 VB100, 0 If receive complete for any other reason, then start a new receive. TBL PORT INTERRUPT 1 Network 1 Timer interrupt. DTCH EN ENO SM0.
SIMATIC Instructions FBD Network 1 MOV_B EN ENO SM0.1 16#9 IN OUT SMB30 16#B0 IN MOV_W EN ENO +5 IN OUT MOV_B EN ENO MOV_B EN ENO OUT SMB87 16#A 100 IN OUT OUT SMB89 ATCH EN ENO MOV_B EN ENO SMW90 IN SMB94 0 INT 23 EVNT ATCH EN ENI ENO 2 INT 9 EVNT RCV EN VB100 ENO TBL 0 PORT INTERRUPT 0 Network 1 ==B SMB86 16#20 10 MOV_B EN ENO IN OUT SMB34 1 10 ATCH EN ENO INT RETI EVNT RCV EN ENO VB100 0 TBL PORT INTERRUPT 1 DTCH SM0.
SIMATIC Instructions 9.17 SIMATIC Logic Stack Instructions And Load S T L ALD 3 221 3 222 3 224 The And Load instruction combines the values in the first and second levels of the stack using a logical And operation. The result is loaded in the top of stack. After the ALD is executed, the stack depth is decreased by one. Operands: none Or Load S T L OLD 3 221 3 222 3 224 The Or Load instruction combines the values in the first and second levels of the stack, using a logical Or operation.
SIMATIC Instructions Logic Pop S T L The Logic Pop instruction pops one value off of the stack. The second stack value becomes the new top of stack value. LPP 3 221 3 222 3 Operands: none 224 Load Stack S T L LDS 3 221 3 222 n 3 The Load Stack instruction duplicates the stack bit n on the stack and places this value on top of the stack. The bottom of the stack is pushed off and lost.
SIMATIC Instructions Figure 9-76 illustrates the operation of the Logic Push, Logic Read, and Logic Pop instructions.
SIMATIC Instructions LAD STL Network 1 I0.0 I2.0 NETWORK 1 LD I0.0 LD I0.1 LD I2.0 A I2.1 OLD ALD = Q5.0 Q5.0 I0.1 I2.1 Network 2 I0.0 I0.5 NETWORK 2 LD I0.0 LPS LD I0.5 O I0.6 ALD = Q7.0 LRD LD I2.1 O I1.3 ALD = Q6.0 LPP A I1.0 = Q3.0 Q7.0 I0.6 I2.1 Q6.0 I1.3 I1.0 Figure 9-78 Q3.0 Example of Logic Stack Instructions for LAD and STL FBD Network 1 AND OR AND I2.0 I2.1 Q5.0 I0.0 I0.1 Network 2 AND AND I0.0 Q7.0 SM0.0 I0.5 OR I0.6 AND Q6.0 I2.1 OR I1.3 AND Q3.0 I1.
SIMATIC Instructions 9-196 S7-200 Programmable Controller System Manual C79000-G7076-C233-01
10 IEC 1131-3 Instructions This chapter describes the standard IEC 1131-3 instructions. There are some SIMATIC instructions that can be used in an IEC program. These instructions are called non-standard IEC instructions, and are shown at the beginning of each section. Chapter Overview Section Description Page 10.1 IEC Bit Logic Instructions 10-2 10.2 IEC Compare Instructions 10-7 10.3 IEC Timer Instructions 10-11 10.4 IEC Counter Instructions 10-15 10.5 IEC Math Instructions 10-19 10.
IEC 1131-3 Instructions 10.1 IEC Bit Logic Table 10-1 gives page references for the non-standard IEC Bit Logic instructions.
IEC 1131-3 Instructions Positive, Negative Transition The Positive Transition contact allows power to flow for one scan for each off-to-on transition. L A D P The Negative Transition contact allows power to flow for one scan, for each on-to-off transition. N F B D In LAD, the Positive and Negative Transition instructions are represented by contacts. P IN OUT In FBD, the instructions are represented by the POS and NEG boxes.
IEC 1131-3 Instructions Output L A D bit When the Output is executed, the output is turned on. In LAD, the Output instruction is represented by a coil. In FBD, the instruction is represented by the = box.
IEC 1131-3 Instructions Output Examples LAD Network 1 %I0.0 %Q0.0 %Q0.1 S %Q0.2 R %Q0.3 R FBD Network 1 AND %I0.0 %SM0.0 %Q0.0 = %Q0.1 S %Q0.2 R %Q0.3 R Timing Diagram I0.0 Q0.0 Q0.1 Q0.2 Q0.
IEC 1131-3 Instructions Set Dominant Bistable L A D L A D F B D xxx SR S1 OUT The xxx function block parameter specifies the Boolean parameter that is set or reset. The optional output reflects the signal state of the xxx parameter. R 3 221 3 222 The Set Dominant Bistable is a latch where the set dominates. If the set (S1) and reset (R) signals are both true, the output (OUT) will be true.
IEC 1131-3 Instructions 10.2 IEC Compare Instructions There are no non-standard IEC Compare instructions. Compare Equal L A D EQ EN OUT IN1 IN2 F B D The Compare Equal function compares IN1 and IN2 with the Boolean result placed in OUT. The input and output data types can vary but must be of the same type. Byte comparisons are unsigned. Integer, double integer, and real comparisons are signed.
IEC 1131-3 Instructions Compare Not Equal L A D NE EN OUT IN1 IN2 F B D The Compare Not Equal function compares IN1 and IN2 with the Boolean result placed in OUT. The input and output data types can vary, but must be of the same type. Byte comparisons are unsigned. Integer, double integer, and real comparisons are signed.
IEC 1131-3 Instructions Compare Less Than or Equal L A D LE EN OUT IN1 IN2 The Compare Less Than or Equal function compares IN1 less than or equal to IN2 with the Boolean result placed in OUT. The input and output data types can vary, but they must be of the same type. Byte comparisons are unsigned. Integer, double integer, and real comparisons are signed.
IEC 1131-3 Instructions Compare Greater Than or Equal L A D GE EN OUT IN1 IN2 The Compare Greater Than or Equal function compares IN1 greater than or equal to IN2 with the Boolean result placed in OUT. The input and output data types can vary, but they must be of the same type. Byte comparisons are unsigned. Integer, double integer, and real comparisons are signed.
IEC 1131-3 Instructions 10.3 IEC Timer Instructions Table 10-2 gives page references for the non-standard IEC Timer instructions. Table 10-2 Non-Standard IEC Timer Instructions Description Page Retentive On-Delay Timer Instruction 9-15 On-Delay Timer L A D xxx TON IN PT Q ET F B D 3 221 3 222 3 224 The On-Delay Timer function block times up to the preset value when the enabling input (IN) becomes true.
IEC 1131-3 Instructions Off-Delay Timer L A D xxx IN TOF Q PT F B D ET 3 221 3 222 The Off-Delay Timer function block is used to delay the setting of an output false for a fixed period of time after the input goes false. It times up to the preset value when the enabling input (IN) goes false. When the elapsed time (ET) is greater than or equal to the preset time (PT), the timer output bit (Q) turns on.
IEC 1131-3 Instructions Understanding the IEC 1131-3 Timer Instructions TON, TOF and TP timers are available in three resolutions. The resolution is determined by the timer number and is shown in Table 10-3. Each count of the current value is a multiple of the time base. For example, a count of 50 on a 10-ms timer represents 500 ms. Table 10-3 Timer Numbers and Resolutions Resolution in milliseconds (ms) Timer Type TON, TOF, TP Maximum Value in seconds (s) Timer Number 1 ms 32.
IEC 1131-3 Instructions Off-Delay Timer Example LAD FBD T33 Input Input IN 3 PT TOF 3 IN PT Q Output ET %VW100 T33 TOF Q Output ET %VW100 Timing Diagram Input VW100 (current) PT = 3 PT = 3 Output (Q) Figure 10-4 Example of Off-Delay Timer for LAD and FBD Pulse Timer Example LAD FBD T33 Input 3 IN PT TP Q ET Output %VW100 Input IN 3 PT T33 TON Q ET Output %VW100 Timing Diagram Input VW100 (current) PT = 3 Output Figure 10-5 10-14 Example of Pulse Timer Instruction for LAD an
IEC 1131-3 Instructions 10.4 IEC Counter Instructions Table 10-4 gives page references for the non-standard IEC Counter instructions.
IEC 1131-3 Instructions Down Counter L A D CD LD F B D xxx CTD Q CV PV 3 221 3 222 The Down Counter function block counts down from the preset value on the rising edges of the Count Down (CD) input. When the current value (CV) is equal to zero, the counter output bit (Q) turns on. The counter resets and loads the current value (CV) with the preset value (PV) when the load input (LD) is enabled. The Down Counter stops counting when it reaches zero.
IEC 1131-3 Instructions Up/Down Counter xxx L A D CTUD CD CU R LD QU PV QD F B D CV 3 221 3 222 3 The Up/Down Counter function block counts up or down from the preset value on the rising edges of the Count Up (CU) or Count Down (CD) input. When the current value (CV) is equal to preset, the output (QU) turns on. When the current value (CV) is equal to zero, the output (QD) turns on. The counter loads the current value (CV) with the preset value (PV) when the load (LD) input is enabled.
IEC 1131-3 Instructions Counter Example LAD FBD C48 CTUD CU %I4.0 I4.0 C48 CTUD CU I3.0 CD I2.0 R %I3.0 CD %I2.0 R %I1.0 4 LD PV QU QD CV %I1.0 LD 4 PV %Q0.0 %Q0.1 %VW0 QU QD CV %Q0.0 %Q0.1 %VW0 Timing Diagram I4.0 CU-Up I3.0 CD-Down I2.0 R-Reset I1.0 LD-Load 4 3 2 VW0 CV-current 0 4 4 4 3 3 2 1 0 Q0.0 QU-Up QD.
IEC 1131-3 Instructions 10.5 IEC Math Instructions Table 10-6 gives page references for the non-standard IEC Math instructions. Table 10-6 Non-Standard IEC Math Instructions Description PID Instruction Page 9-84 Add, Subtract L A D ADD ENO EN F B D IN1 OUT OUT IN2 EN SUB ENO The Add and Subtract functions add or subtract IN1 and IN2 and place the result in OUT. The input and output data types can vary, but must be of the same type.
IEC 1131-3 Instructions Multiply, Divide L A D EN F B D MUL ENO IN1 OUT OUT IN1 OUT OUT IN2 In LAD: EN 221 The Divide function divides IN1 by IN2 and places the result in the variable specified by OUT. The input and output data types can vary, but must be of the same type. For example, the product of multiplying two 16-bit variables must be placed in a 16-bit variable, the product of multiplying two 32-bit variables must be placed in a 32-bit variable.
IEC 1131-3 Instructions Math Examples LAD Network 1 %I0.0 EN ADD ENO %AC1 IN1 OUT OUT MUL EN %AC0 %AC1 IN1 OUT OUT %AC0 IN2 DIV ENO EN ENO %VD100 %VW102 IN2 %VW202 IN1 OUT OUT %VW10 %VD200 IN2 FBD Network 1 %I0.
IEC 1131-3 Instructions Square Root L A D SQRT EN ENO F B D IN 3 221 3 222 OUT 3 The Square Root function takes the square root of a value provided by IN and places the result in OUT. Error conditions that set ENO = 0: SM1.1 (overflow), SM4.3 (run-time), 0006 (indirect address) This function affects the following Special Memory bits: SM1.0 (zero); SM1.1 (overflow); SM1.2 (negative) 224 If SM1.
IEC 1131-3 Instructions Increment, Decrement Example LAD I4.0 AC0 EN INC ENO IN OUT AC0 VD100 EN DEC ENO IN OUT VD100 FBD I4.
IEC 1131-3 Instructions 10.6 IEC Move Instructions Table 10-7 gives page references for the non-standard IEC Move instructions. Table 10-7 Non-Standard IEC Move Instructions Description Page Swap Instructions 9-102 Move L A D MOVE EN ENO F B D IN 3 221 3 222 OUT 3 The Move and Assign Values function moves the value IN to the address OUT. This instruction performs an assignment operation. The input parameter is not modified during execution.
IEC 1131-3 Instructions Block Move L A D BLKMOVE EN ENO F B D IN The Block Move function moves the N number of words specified by the address IN to the address OUT. N has a range of 1 to 255. The input and output data types can vary, but must be of the same type. OUT N Block Move is a non-standard IEC-only function. 3 3 3 221 222 224 Error conditions that set ENO = 0: SM4.
IEC 1131-3 Instructions 10.7 IEC Logic Instructions There are no non-standard IEC Logic instructions. And, Or, Exclusive Or L A D AND ENO EN F B D IN1 OUT IN2 OR ENO EN IN1 OUT IN2 EN The And function ANDs the corresponding bits of IN1 and IN2 and loads the result into OUT. The Or function ORs the corresponding bits of IN1 with IN2 and loads the result into OUT. The Exclusive Or (XOR) function XORs the corresponding bits of IN1 with IN2 and loads the result into OUT.
IEC 1131-3 Instructions And, Or, and Exclusive Or Example LAD %I4.0 %AC1 %VW90 AND ENO EN IN1 OUT %VW90 IN2 EN OR ENO %AC1 IN1 %VW100 IN2 EN OUT %VW100 XOR ENO %AC1 IN1 %VW200 IN2 OUT %VW200 FBD %I4.
IEC 1131-3 Instructions Not L A D F B D 3 221 Inputs/Outputs EN NOT NOT ENO IN OUT 3 222 3 224 The Not function inverts the corresponding bits of IN and loads the result into OUT. The input and output data types can vary, but must be of the same type. Error conditions that set ENO = 0: SM4.3 (run-time), 0006 (indirect address) This instruction affects the following Special Memory bits: SM1.
IEC 1131-3 Instructions 10.8 IEC Shift and Rotate Instructions Table 10-8 gives page references for the non-standard IEC Shift instructions. Table 10-8 Non-Standard IEC Instructions Description Page Shift Register Bit Instruction 9-123 Logical Shift Right, Logical Shift Left L A D F B D EN SHR ENO IN OUT N EN SHL ENO IN OUT 3 3 222 The Shift Left function shifts the value specified by the variable IN to the left for the number of locations specified by N.
IEC 1131-3 Instructions Logical Rotate Right, Logical Rotate Left L A D ROR EN ENO F B D IN OUT OUT N EN ROL ENO IN OUT OUT The Rotate Right and Rotate Left functions rotate the input value (IN) right or left by the shift count (N), and load the result in the output (OUT). The rotate is circular. In ROR, bit zero is rotated to the most significant bit. In ROL, the most significant bit is rotated to bit zero. Error conditions that set ENO = 0: SM4.
IEC 1131-3 Instructions Shift and Rotate Examples LAD %I4.0 FBD ROR EN ENO %VW100 2 IN OUT %I4.0 EN ROR ENO %VW100 IN OUT %VW100 N SHL EN ENO %VW200 3 IN %VW100 %VW200 3 2 N OUT EN SHL ENO IN OUT %VW200 N %VW200 N Application Rotate Before rotate VW100 0100 0000 0000 0001 After first rotate VW100 1010 0000 0000 0000 After second rotate VW100 0101 0000 0000 0000 Zero Memory Bit (SM1.0) Overflow Memory Bit (SM1.
IEC 1131-3 Instructions 10.9 IEC Conversion Instructions Table 10-9 gives page references for the non-standard IEC Conversion instructions.
IEC 1131-3 Instructions Binary Coded Decimal to Integer, Integer to BCD L A D F B D BCD_TO_I EN ENO IN OUT I_TO_BCD EN ENO IN 3 221 3 222 The BCD to Integer function converts the input Binary-Coded Decimal value (IN) to an integer value and loads the result into the variable specified by OUT. OUT 3 The Integer to BCD function converts the input integer value to a Binary-Coded Decimal value and loads the result in OUT. Error conditions that set ENO = 0: SM1.6 (BCD), SM4.
IEC 1131-3 Instructions Real To Double Integer L A D R_TO_DI EN ENO F B D IN 3 221 3 222 OUT The Real To Double Integer function converts a real value (N) to a double Integer value and loads the result into the variable specified by OUT. Error conditions that set ENO = 0: SM1.1 (overflow), SM4.
IEC 1131-3 Instructions Integer to Double Integer L A D I_TO_DI EN ENO F B D IN 3 221 3 222 The Integer to Double Integer function converts the integer value specified by IN to a double integer value and loads the result into the variable specified by OUT. OUT 3 Error conditions that set ENO = 0: SM4.
IEC 1131-3 Instructions Integer to Byte L A D The Integer to Byte function converts the integer value (IN) to a byte value and loads the result into the variable specified by OUT. I_TO_B EN ENO F B D IN 3 3 221 222 OUT Error conditions that set ENO = 0: SM1.1 (overflow), SM4.3 (run-time), 0006 (indirect address) 3 This function affects the following Special Memory bits: SM1.1 (overflow).
IEC 1131-3 Instructions FBD Network 1 %I0.0 I_TO_DI EN ENO %VW20 IN DI_TO_R EN ENO OUT %AC1 %AC1 IN OUT EN MUL ENO %VD0 %VD0 IN1 OUT %VD4 IN2 ROUND EN ENO %VD8 %VD8 IN OUT %VD12 Network 2 %I3.0 %VW100 BCD_TO-I ENO EN IN OUT %VW100 Application Double Integer Integer to Real and Truncate VW20 101 BCD to Integer Count = 101 inches VD0 101.0 VD4 2.54 VD8 256.54 V12 257 VW100 1234 2.54 constant (inches to centimeters) 256.
IEC 1131-3 Instructions 10-38 S7-200 Programmable Controller System Manual C79000-G7076-C233-01
A S7-200 Specifications Chapter Overview Section Description Page A.1 General Technical Specifications A-2 A.2 Specifications for the CPU 221 A-6 A.3 Specifications for the CPU 222 A-11 A.4 Specifications for the CPU 224 A-16 A.5 Specifications for the EM221 Digital Input Module A-21 A.6 Specifications for the EM222 Digital Output Modules A-23 A.7 Specifications for the EM223 Digital Combination Modules, 8 Inputs/8 Outputs A-25 A.8 Optional Cartridges A-28 A.
S7-200 Specifications A.1 General Technical Specifications National and International Standards The national and international standards listed below were used to determine appropriate performance specifications and testing for the S7-200 family of products. Table A-1 defines the specific adherence to these standards. Underwriters Laboratories, Inc.: UL 508 Listed (Industrial Control Equipment) Canadian Standards Association: CSA C22.
S7-200 Specifications Technical Specifications The S7-200 CPUs and all S7-200 expansion modules conform to the technical specifications listed in Table A-1.
S7-200 Specifications Table A-1 Technical Specifications for the S7-200 Family Electromagnetic Compatibility — Conducted and Radiated Emissions per EN50081 -12 and -2 EN 55011, Class A, Group 1, conducted1 0.15 MHz to 0.5 MHz < 79 dB (µV) Quasi-peak; < 66 dB (µV) Average 0.
S7-200 Specifications Relay Electrical Service Life Figure A-1 shows typical performance data supplied by relay vendors. Actual performance may vary depending upon your specific application. 4000 250 VAC resistive load 30 VDC resistive load 1000 500 300 100 250 VAC inductive load (p.f.=0.
S7-200 Specifications A.
S7-200 Specifications Table A-2 Specifications for CPU 221 DC/DC/DC and CPU 221 AC/DC/Relay Description Order Number CPU 221 DC/DC/DC 6ES7 211-0AA20-0XBO CPU 221 AC/DC/Relay 6ES7 211-0BA20-0XB0 On-board Communication Number of ports 1 port 1 port Electrical interface RS-485 RS-485 Isolation (external signal to logic circuit) Not isolated Not isolated PPI/MPI baud rates 9.6, 19.2, and 187.5 kbaud 9.6, 19.2, and 187.5 kbaud Freeport baud rates 0.3, 0.6, 1.2, 2.4, 4.8, 9.6, 19.2, and 38.
S7-200 Specifications Table A-2 Specifications for CPU 221 DC/DC/DC and CPU 221 AC/DC/Relay Description Order Number CPU 221 DC/DC/DC 6ES7 211-0AA20-0XBO CPU 221 AC/DC/Relay 6ES7 211-0BA20-0XB0 Input Features Number of integrated inputs 6 inputs 6 inputs Input type Sink/Source (IEC Type 1 sink) Sink/Source (IEC Type 1 sink) Maximum continuous permissible 30 VDC 30 VDC Surge 35 VDC for 0.5 s 35 VDC for 0.
S7-200 Specifications Table A-2 Specifications for CPU 221 DC/DC/DC and CPU 221 AC/DC/Relay Description Order Number CPU 221 DC/DC/DC 6ES7 211-0AA20-0XBO CPU 221 AC/DC/Relay 6ES7 211-0BA20-0XB0 Isolation Optical isolation (galvanic) 500 VAC for 1 minute Isolation resistance - 100 M Ω, minimum when new Isolation coil to contact - 1500 VAC for 1 minute Isolation between open contacts - 750 VAC for 1 minute In groups of 4 points 3 points and 1 point 1 W, all channels - L+ minus 48 V - 2
S7-200 Specifications 24 VDC Power, Ground and Output Terminals + M L+ Note: 1. Actual component values may vary. 2. Either polarity accepted. 3. Optional ground. 0.0 0.1 0.2 0.3 24 VDC Power Supply Input + M L+DC M L+ 36V 5.6K Ω 1K Ω 1M 0.0 0.1 0.2 0.3 2M 0.4 0.
S7-200 Specifications A.
S7-200 Specifications Table A-3 Specifications for CPU 222 DC/DC/DC and CPU 222 AC/DC/Relay Description Order Number CPU 222 DC/DC/DC 6ES7 212-1AB20-0XB0 CPU 222 AC/DC/Relay 6ES7 212-1BB20-0XB0 On-board Communication Number of ports 1 port 1 port Electrical interface RS-485 RS-485 Isolation (external signal to logic circuit) Not isolated Not isolated PPI/MPI baud rates 9.6, 19.2, and 187.5 kbaud 9.6, 19.2, and 187.5 kbaud Freeport baud rates 0.3, 0.6, 1.2, 2.4, 4.8, 9.6, 19.2, and 0.3, 0.
S7-200 Specifications Table A-3 Specifications for CPU 222 DC/DC/DC and CPU 222 AC/DC/Relay Description Order Number CPU 222 DC/DC/DC 6ES7 212-1AB20-0XB0 CPU 222 AC/DC/Relay 6ES7 212-1BB20-0XB0 Input Features Number of integrated inputs 8 inputs 8 inputs Input type Sink/Source (IEC Type 1 sink) Sink/Source (IEC Type 1 sink) Maximum continuous permissible 30 VDC 30 VDC Surge 35 VDC for 0.5 s 35 VDC for 0.
S7-200 Specifications Table A-3 Specifications for CPU 222 DC/DC/DC and CPU 222 AC/DC/Relay Description Order Number CPU 222 DC/DC/DC 6ES7 212-1AB20-0XB0 CPU 222 AC/DC/Relay 6ES7 212-1BB20-0XB0 Isolation Optical isolation (galvanic) 500 VAC for 1 minute Isolation resistance - 100 M Ω, minimum when new Isolation coil to contact - 1500 VAC for 1 minute Isolation between open contacts - 750 VAC for 1 minute In groups of 6 points 3 points 1 W, all channels - L+ minus 48V - 2 µs, maximum
S7-200 Specifications 24 VDC Power, Ground and Output Terminals + + M 24 VDC Power Supply Input L+ Note: 1. Actual component values may vary. 2. Either polarity accepted. 3. Optional ground. 0.0 0.1 0.2 0.3 0.4 0.5 M L+DC 36V 1K Ω 1M 0.0 0.1 0.2 0.3 5.6K Ω 2M 0.4 0.5 0.6 0.
S7-200 Specifications A.4 Specifications for the CPU 224 Table A-4 Specifications for CPU 224 DC/DC/DC and CPU 224 AC/DC/Relay Description Order Number CPU 224 DC/DC/DC 6ES7 214-1AD20-0XB0 CPU 224 AC/DC/Relay 6ES7 214-1BD20-0XB0 Physical Size Dimensions (W x H x D) 120.5 mm x 80 mm x 62 mm 120.
S7-200 Specifications Table A-4 Specifications for CPU 224 DC/DC/DC and CPU 224 AC/DC/Relay Description Order Number CPU 224 DC/DC/DC 6ES7 214-1AD20-0XB0 CPU 224 AC/DC/Relay 6ES7 214-1BD20-0XB0 On-board Communication Number of ports 1 port 1 port Electrical interface RS-485 RS-485 Isolation (external signal to logic circuit) Not isolated Not isolated PPI/MPI baud rates 9.6, 19.2, and 187.5 kbaud 9.6, 19.2, and 187.5 kbaud Freeport baud rates 0.3, 0.6, 1.2, 2.4, 4.8, 9.6, 19.2, and 38.
S7-200 Specifications Table A-4 Specifications for CPU 224 DC/DC/DC and CPU 224 AC/DC/Relay Description Order Number CPU 224 DC/DC/DC 6ES7 214-1AD20-0XB0 CPU 224 AC/DC/Relay 6ES7 214-1BD20-0XB0 Input Features Number of integrated inputs 14 inputs 14 inputs Input type Sink/Source (IEC Type 1) Sink/Source (IEC Type 1) Maximum continuous permissible 30 VDC 30 VDC Surge 35 VDC for 0.5 s 35 VDC for 0.
S7-200 Specifications Table A-4 Specifications for CPU 224 DC/DC/DC and CPU 224 AC/DC/Relay Description Order Number CPU 224 DC/DC/DC 6ES7 214-1AD20-0XB0 CPU 224 AC/DC/Relay 6ES7 214-1BD20-0XB0 Isolation (Field Side to Logic) Optical isolation (galvanic) 500 VAC for 1 minute Isolation resistance - 100 M Ω, minimum when new Isolation coil to contact - 1500 VAC for 1 minute Isolation between open contacts - 750 VAC for 1 minute In groups of 5 points 4 points/3 points/3 points 1 W, all chann
S7-200 Specifications 24 VDCPower 24 VDC Power, Ground and Output Terminals Note: 1. Actual component values may vary. 2. Either polarity accepted. 3. Optional ground. 1M Figure A-6 0.0 0.0 0.1 0.2 0.3 0.4 2M 2L+ 0.5 0.6 0.7 1.0 1.1 + + 1M 1L+ 24 VDC Common and 24 VDC Input Terminals + M L+DC 36V 1K Ω 0.1 0.2 0.3 0.4 0.5 0.6 0.7 + 5.6K Ω 2M 1.0 1.1 1.2 1.3 Sensor Power Output 1.4 1.
S7-200 Specifications A.5 Table A-5 Specifications for the EM221 Digital Input Module Specifications for EM221 24 VDC, 8 Digital Input Module Description Order Number EM221 24 VDC, 8 Input 6ES7 221-1BF20-0XA0 Physical Size Dimensions (W x H x D) 46 x 80 x 62 mm Weight 150 g Power loss (dissipation) 2W Input Features Number of integrated inputs 8 inputs Input type Sink/Source (IEC Type 1 sink) Input Voltage Maximum continuous permissible 30 VDC Surge 35 VDC for 0.
S7-200 Specifications + 24 VDC common and 24 VDC Input Terminals 1M Note: 1. Actual component values may vary. 2. Either polarity accepted. 3. Optional ground. .0 .1 .2 .3 5.6K Ω 1K Ω 2M .4 .5 .6 .
S7-200 Specifications A.6 Table A-6 Specifications for the EM222 Digital Output Modules Specifications for EM222 24 VDC Output and Relay Output Modules Description Order Number EM222 24 VDC Output 6ES7 222-1BF20-0XA0 EM222 Relay Output 6ES7 222-1HF20-0XA0 Physical Size Dimensions (W x H x D) 46 x 80 x 62 mm 46 x 80 x 62 mm Weight 150 g 170 g Power loss (dissipation) 2W 2W Number of outputs 8 points 8 points Output type Solid state-MOSFET Relay, dry contact Permissible range 20.
S7-200 Specifications + 24 VDC Commons and 24 VDC Output Terminals 1M 1L+ .0 Note: 1. Actual component values may vary. 2. Optional ground. .1 .2 .3 .5 .6 .7 36V 2M 24 VDC Commons and 24 VDC Output Terminals 2L+ .4 + Figure A-9 Connector Terminal Identification for EM222 Digital Output 8 x 24 VDC N (-) L (+) 24 VDC Power Commons and Relay Output Terminals Note: 1. Actual component values may vary. 2. Connect AC line to the L terminal. 3. Optional ground. 4.
S7-200 Specifications A.7 Table A-7 Specifications for the EM223 Digital Combination Modules, 8 Inputs/8 Outputs Specifications for EM223 24 VDC 8 In/8 Out, and EM223 24 VDC 8 In/8 Relay Out Description Order Number EM223 24VDC In/Out 6ES7 223-1BH20-0XA0 EM223 24VDC In/Relay Out 6ES7 223-1PH20-0XA0 Physical Size Dimensions (W x H x D) 71.2 mm x 80 mm x 62 mm 71.
S7-200 Specifications Table A-7 Specifications for EM223 24 VDC 8 In/8 Out, and EM223 24 VDC 8 In/8 Relay Out Description Order Number EM223 24VDC In/Out 6ES7 223-1BH20-0XA0 EM223 24VDC In/Relay Out 6ES7 223-1PH20-0XA0 Output Current Logic 1 signal 0.75 A 2.
S7-200 Specifications + 24 VDC Commons and 24VDC Output Terminals 1M Note: 1. Actual component values may vary. 2. Either polarity accepted 3. Optional ground. + 1L+ .0 .1 .2 .3 2M 2L+ .4 .5 .6 .7 .6 .7 36V 470 Ω 5.6 KΩ 1M .0 .1 .2 .3 2M .4 .5 24 VDC Commons and 24 VDC Input Terminals + + Figure A-11 Connector Terminal Identification for EM223 Digital Combination 8 x 24 VDC Inputs/8 x 24 VDC Outputs N (-) L (+) Relay Commons and Relay Output Terminals 1L .0 .1 .
S7-200 Specifications A.
S7-200 Specifications A.9 I/O Expansion Cable Order Number: 6ES7 290-6AA20-0XA0 General Features Cable length 0.8 m (32 in.) Weight 25 g (.88 lb.) Connector type 10 pin ribbon Typical Installation of the I/O Expansion Cable Female Connector Male Connector Figure A-13 Typical Installation of an I/O Expansion Cable Note Only one expansion cable should be included in a CPU/expansion module chain.
S7-200 Specifications A.10 PC/PPI Cable Order Number: 6ES7 901-3BF20-0XA0 PC/PPI Cable Dimensions 0.1 m (4 in.) 0.3 m (12 in.) 4.6 m (181 in.) 40 mm (1.6 in.) RS-232 COMM RS-485 COMM Isolated PC/PPI Cable PPI 1 0 Figure A-14 Table A-8 Table A-9 A-30 1 2 3 4 5 Baud Rate 38.4K 19.2K 9.6K 2.4K 1.
S7-200 Specifications Table A-10 Pin-out of PC/PPI Cable Pinout Switch (1 = Up) DCE 0 DTE 1 Table A-11 Pin-outs for RS-485 to RS-232 DCE Connector RS-485 Connector Pin-out Pin Number Signal Description RS-232 DCE Connector Pin-out Pin Number Signal Description 1 Ground (RS-485 logic ground) 1 Data Carrier Detect (DCD) (not used) 2 24 V Return (RS-485 logic ground) 2 Receive Data (RD) (output from PC/PPI cable) 3 Signal B (RxD/TxD+) 3 Transmit Data (TD) (input to PC/PPI cable) 4 RTS (
S7-200 Specifications A-32 S7-200 Programmable Controller System Manual C79000-G7076-C233-01
B Error Codes The information about error codes is provided to help you identify problems with your S7-200 CPU module. Chapter Overview Section Description Page B.1 Fatal Error Codes and Messages B-2 B.2 Run-Time Programming Problems B-3 B.
Error Codes B.1 Fatal Error Codes and Messages Fatal errors cause the CPU to stop the execution of your program. Depending on the severity of the error, a fatal error can render the CPU incapable of performing any or all functions. The objective for handling fatal errors is to bring the CPU to a safe state from which the CPU can respond to interrogations about the existing error conditions.
Error Codes B.2 Run-Time Programming Problems Your program can create non-fatal error conditions (such as addressing errors) during the normal execution of the program. In this case, the CPU generates a non-fatal run-time error code. Table B-2 lists the descriptions of the non-fatal error codes.
Error Codes B.3 Compile Rule Violations When you download a program, the CPU compiles the program. If the CPU detects that the program violates a compile rule (such as an illegal instruction), the CPU aborts the download and generates a non-fatal, compile-rule error code. Table B-3 lists the descriptions of the error codes that are generated by violations of the compile rules.
C Special Memory (SM) Bits Special memory bits provide a variety of status and control functions, and also serve as a means of communicating information between the CPU and your program. Special memory bits can be used as bits, bytes, words, or double words. SMB0: Status Bits As described in Table C-1, SMB0 contains eight status bits that are updated by the S7-200 CPU at the end of each scan cycle. Table C-1 Special Memory Byte SMB0 (SM0.0 to SM0.7) SM Bits Description SM0.0 This bit is always on.
Special Memory (SM) Bits SMB1: Status Bits As described in Table C-2, SMB1 contains various potential error indicators. These bits are set and reset by instructions at execution time. Table C-2 Special Memory Byte SMB1 (SM1.0 to SM1.7) SM Bits Description SM1.0 This bit is turned on by the execution of certain instructions when the result of the operation is zero. SM1.
Special Memory (SM) Bits SMB4: Queue Overflow As described in Table C-5, SMB4 contains the interrupt queue overflow bits, a status indicator showing whether interrupts are enabled or disabled, and a transmitter-idle memory bit. The queue overflow bits indicate either that interrupts are happening at a rate greater than can be processed, or that interrupts were disabled with the global interrupt disable instruction. Table C-5 Special Memory Byte SMB4 (SM4.0 to SM4.7) SM Bits Description SM4.
Special Memory (SM) Bits SMB6: CPU ID Register As described in Table C-7, SMB6 is the CPU identification register. SM6.4 to SM6.7 identify the type of CPU. SM6.0 to SM6.3 are reserved for future use. Table C-7 Special Memory Byte SMB6 Description SM Bits Format MSB 7 x SM6.4 to SM6.7 SM6.0 to SM6.3 LSB 0 x x x xxxx = 0000 = 0010 = 0110 = 1000 = 1001 = r r r r CPU ID register CPU 212/CPU 222 CPU 214/CPU 224 CPU 221 CPU 215 CPU 216 Reserved SMB7: Reserved SMB7 is reserved for future use.
Special Memory (SM) Bits SMB8 to SMB21: I/O Module ID and Error Registers SMB8 through SMB21 are organized in byte pairs for expansion modules 0 to 6. As described in Table C-8, the even-numbered byte of each pair is the module-identification register. These bytes identify the module type, the I/O type, and the number of inputs and outputs. The odd-numbered byte of each pair is the module error register. These bytes provide an indication of any errors detected in the I/O for that module.
Special Memory (SM) Bits SMW22 to SMW26: Scan Times As described in Table C-9, SMW22, SMW24, and SMW26 provide scan time information: minimum scan time, maximum scan time, and last scan time in milliseconds. Table C-9 Special Memory Words SMW22 to SMW26 Description SM Word SMW22 This word provides the scan time of the last scan cycle. SMW24 This word provides the minimum scan time recorded since entering the RUN mode.
Special Memory (SM) Bits Table C-11 Special Memory Byte SMB30 Port 0 Port 1 Format of SMB30 Format of SMB130 Description MSB 7 p LSB 0 p d b b Freeport mode control byte b m m SM30.6 and SM30.7 SM130.6 and SM130.7 pp Parity select 00 = no parity 01 = even parity 10 = no parity 11 = odd parity SM30.5 SM130.5 d Data bits per character 0= 8 bits per character 1= 7 bits per character SM30.2 to SM30.4 SM130.2 to SM130.
Special Memory (SM) Bits As described in Table C-12, SMB31 defines the size of the data to be saved to permanent memory and also provides the command that initiates the execution of a save operation. SMW32 stores the starting address in V memory for the data to be saved to permanent memory.
Special Memory (SM) Bits SMB36 to SMB65: HSC0, HSC1, and HSC2 Register As described in Table C-14, SMB36 through SM65 are used to monitor and control the operation of high-speed counters HSC0, HSC1, and HSC2. Table C-14 Special Memory Bytes SMB36 to SMB65 Description SM Byte SM36.0 to SM36.4 Reserved SM36.5 HSC0 current counting direction status bit: 1 = counting up SM36.6 HSC0 current value equals preset value status bit: 1 = equal SM36.
Special Memory (SM) Bits Table C-14 Special Memory Bytes SMB36 to SMB65 SM Byte Description SM47.7 HSC1 enable bit: 1 = enable SMB48 HSC1 new current value SMB49 SMB48 is most significant byte, and SMB51 is least significant byte. SMB50 SMB51 SMB52 to HSC1 new preset value SMB55 SMB52 is most significant byte, and SMB55 is least significant byte. SM56.0 to SM56.4 Reserved SM56.5 HSC2 current counting direction status bit: 1 = counting up SM56.
Special Memory (SM) Bits SMB66 to SMB85: PTO/PWM Registers As described in Table C-15, SMB66 through SMB85 are used to monitor and control the pulse train output and pulse width modulation functions. See the information on high-speed output instructions in Section 9.5 in Chapter 9 for a complete description of these bits. Table C-15 Special Memory Bytes SMB66 to SMB85 Description SM Byte SM66.0 to SM66.3 Reserved SM66.
Special Memory (SM) Bits Table C-15 Special Memory Bytes SMB66 to SMB85 SM Byte Description SM76.6 PTO1 pipeline overflow (cleared by the system when using external profiles, otherwise must be reset by the user); 0 = no overflow, 1 = pipeline overflow SM76.7 PTO1 idle bit: 0 = PTO in progress, 1 = PTO idle SM77.0 PTO1/PWM1 update the cycle time value: 1 = write new cycle time SM77.1 PWM1 update the pulse width value: 1 = write new pulse width SM77.
Special Memory (SM) Bits Table C-16 Special Memory Bytes SMB86 to SMB94, and SMB186 to SMB194 Port 0 Port 1 SMB87 SMB187 Description MSB 7 n LSB 0 x y z m t bk 0 Receive Message control byte n: 0 = Receive Message function is disabled. 1 = Receive Message function is enabled. The enable/disable receive message bit is checked each time the RCV instruction is executed. x: 0 = Ignore SMB88 or SMB188. 1 = Use the value of SMB88 or SMB188 to detect start of message. y: 0 = Ignore SMB89 or SMB189.
Special Memory (SM) Bits Table C-16 Special Memory Bytes SMB86 to SMB94, and SMB186 to SMB194 Port 0 Port 1 Description SMB89 SMB189 End of message character SMB90 SMB91 SMB190 Idle line time period given in milliseconds. The first character received SMB191 after idle line time has expired is the start of a new message. SM90 (or SM190) is the most significant byte and SM91 (or SM191) is the least significant byte. SMB92 SMB93 SMB192 Inter-character/message timer time-out value (in milliseconds).
Special Memory (SM) Bits SMB131 to SMB165: HSC3, HSC4, and HSC5 Register As described in Table C-18, SMB131 through SMB165 are used to monitor and control the operation of high-speed counters HSC3, HSC4, and HSC5. Table C-18 Special Memory Bytes SMB130 to SMB165 Description SM Byte SMB131 to SMB135 Reserved SM136.0 to SM136.4 Reserved SM136.5 HSC3 current counting direction status bit: 1 = counting up SM136.6 HSC current value equals preset value status bit: 1 = equal SM136.
Special Memory (SM) Bits Table C-18 Special Memory Bytes SMB130 to SMB165 SM Byte Description SM156.0 to SM156.4 Reserved SM156.5 HSC5 current counting direction status bit: 1 = counting up SM156.6 HSC5 current value equals preset value status bit: 1 = equal SM156.7 HSC5 current value is greater than preset value status bit: 1 = greater than SM157.0 to SM157.2 Reserved SM157.3 HSC5 direction control bit: 1 = count up SM157.4 HSC5 update direction: 1 = update direction SM157.
D S7-200 Troubleshooting Guide Table D-1 S7-200 Troubleshooting Guide Possible Causes Problem Outputs stop working. CPU SF (System Fault) light comes on. Solution The device being controlled has caused an electrical surge that damaged the output. When connecting to an inductive load (such as a motor or relay), a proper suppression circuit should be used. Refer to Section 2.4.
S7-200 Troubleshooting Guide Table D-1 S7-200 Troubleshooting Guide Problem Possible Causes Solution Communication network is damaged when connecting to an external device. The communication cable can provide a path for unwanted currents if all non-isolated devices (such as PLCs, computers or other devices) that are connected to the network do not share the same circuit common reference. The unwanted currents can cause communication errors or damage to the circuits.
S7-200 Order Numbers CPUs E Order Number CPU 221 DC/DC/DC 6 Inputs/4 Outputs 6ES7 211-0AA20-0XB0 CPU 221 AC/DC/Relay 6 Inputs/4 Outputs 6ES7 211-0BA20-0XB0 CPU 222 DC/DC/DC 8 Inputs/6 Outputs 6ES7 212-1AB20-0XB0 CPU 222 AC/DC/Relay 8 Inputs/6 Outputs 6ES7 212-1BB20-0XB0 CPU 224 DC/DC/DC 14 Inputs/10 Outputs 6ES7 214-1AD20-0XB0 CPU 224 AC/DC/Relay 14 Inputs/10 Outputs 6ES7 214-1BD20-0XB0 Expansion Modules Order Number EM221 24 VDC Digital 8 Inputs 6ES7 221-1BF20-0XA0 EM222 24 VDC Digital 8
S7-200 Order Numbers Manuals Order Number TD 200 Operator Interface User Manual 6ES7 272-0AA00-8BA0 S7-200 Point-to-Point Interface Communication Manual (English/German) 6ES7 298-8GA00-8XH0 S7-200 Programmable Controller System Manual (German) 6ES7 298-8FA20-8AH0 S7-200 Programmable Controller System Manual (English) 6ES7 298-8FA20-8BH0 S7-200 Programmable Controller System Manual (French) 6ES7 298-8FA20-8CH0 S7-200 Programmable Controller System Manual (Spanish) 6ES7 298-8FA20-8DH0 S7-200 Pr
F Execution Times for STL Instructions Effect of Power Flow on Execution Times The calculation of the basic execution time for an STL instruction (Table F-4) shows the time required for executing the logic, or function, of the instruction when power flow is present (where the top-of-stack value is ON or 1).
Execution Times for STL Instructions Execution Times Accessing certain memory areas, such as AI, AQ, L, and accumulators, require additional execution time. Table F-3 provides a factor to be added to the basic execution time for each operand access of these memory areas. Table F-3 Execution Time Adder for Accesses to Selected Memory Areas Memory Area S7-200 CPU Analog Inputs (AI) 149 µs Analog Outputs (AQ) 73 µs Local memory (L) 5.4 µs Accumulators (AC) 4.
Execution Times for STL Instructions Table F-4 Execution Times for the STL Instructions (in µs) Instruction Description A Basic execution time: AB < =, =, >=, >, <, <> Basic execution time 35 AD < =, =, >=, >, <, <> Basic execution time 53 AI Basic execution time: ALD Basic execution time AN Basic execution time: ANDB Basic execution time 37 ANDD Basic execution time 55 ANDW Basic execution time 48 ANI Basic execution time: AR <=, =, >=, >, <, <> Basic execution time 54 ATCH
Execution Times for STL Instructions Table F-4 Execution Times for the STL Instructions (in µs) Instruction CALL CRET S7-200 CPU (in µs) Description With no parameters: Execution time With parameters: Total execution time = Basic time + Σ (input operand handling time) Basic execution time Input operand handling time (bit operand) Input operand handling time (byte operand) Input operand handling time (word operand) Input operand handling time (Dword operand) 15 32 23 21 24 27 Total execution time =
Execution Times for STL Instructions Table F-4 Execution Times for the STL Instructions (in µs) Instruction Description S7-200 CPU (in µs) Total = Basic time + (LM) < (Length) Basic execution time (constant length) Basic execution time (variable length) Length multiplier (LM) 156 165 7 Total = Basic time + (LM) < (Length) Basic execution time Length multiplier (LM) 224 12 Total = Basic time + (LM) < (Number of repetitions) Basic execution time Loop multiplier (LM) 73 72 HDEF Basic execution tim
Execution Times for STL Instructions Table F-4 Execution Times for the STL Instructions (in µs) Instruction S7-200 CPU (in µs) Description LDW <=, =, >=, >, <, <> Basic execution time 42 LIFO Basic execution time 121 LPP Basic execution time 0.37 LPS Basic execution time 0.37 LRD Basic execution time 0.37 LSCR Basic execution time 12 MEND Basic execution time 0.
Execution Times for STL Instructions Table F-4 Execution Times for the STL Instructions (in µs) Instruction PID PLS R Description S7-200 CPU (in µs) Basic execution time 750 Adder to recalculate (Kc
Execution Times for STL Instructions Table F-4 Execution Times for the STL Instructions (in µs) Instruction RRB RRD RRW S S7-200 CPU (in µs) Description Total = Basic time + (LM)<(Length) Basic execution time Length multiplier (LM) 42 0.6 Total = Basic time + (LM)<(Length) Basic execution time Length multiplier (LM) 52 2.5 Total = Basic time + (LM)<(Length) Basic execution time Length multiplier (LM) 49 1.7 For length = 1 and specified as a constant (e.g., S V0.
Execution Times for STL Instructions Table F-4 Execution Times for the STL Instructions (in µs) Instruction SRD Description S7-200 CPU (in µs) Total = Basic time + (LM)<(Length) Basic execution time Length multiplier (LM) 53 2.6 Total = Basic time + (LM)<(Length) Basic execution time Length multiplier (LM) 51 1.
Execution Times for STL Instructions F-10 S7-200 Programmable Controller System Manual C79000-G7076-C233-01
S7-200 Quick Reference Information G This appendix contains information about the following: Special Memory Bits Descriptions of Interrupt Events Summary of S7-200 CPU Memory Ranges and Features HIgh-Speed Counters HSC0, HSC1, HSC2, HSC3, HSC4, HSC5 S7-200 Instructions Table G-1 Special Memory Bits Special Memory Bits SM0.0 Always On SM1.0 Result of operation = 0 SM0.1 First Scan SM1.1 Overflow or illegal value SM0.2 Retentive data lost SM1.2 Negative result SM0.3 Power up SM1.
S7-200 Quick Reference Information Table G-2 Descriptions of Interrupt Events Event Number G-2 Interrupt Description Priority Group Priority in Group 8 Port 0: Receive character 0 9 Port 0: Transmit complete 0 23 Port 0: Receive message complete 24 Port 1: Receive message complete 25 Port 1: Receive character 1 26 Port 1: Transmit complete 1 0 Rising edge, I0.0 2 Rising edge, I0.1 1 4 Rising edge, I0.2 2 6 Rising edge, I0.3 3 1 Falling edge, I0.0 4 3 Falling edge, I0.
S7-200 Quick Reference Information ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ Á
S7-200 Quick Reference Information Table G-4 High-Speed Counters HSC0, HSC3, HSC4, and HSC5 HSC0 Mode HSC3 HSC4 I0.0 I0.1 I0.2 I0.1 I0.3 I0.4 I0.5 I0.
S7-200 Quick Reference Information ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ
S7-200 Quick Reference Information ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
Index A AC installation, guidelines, 2-13 AC outputs, 2-17 Access restriction.
Index Boolean contact instructions, example, 9-5, 10-3 Bus connector, removing expansion modules, 2-8 Byte, and integer range, 5-4 Byte access, 5-2 CPU 221/222/224, 8-8 using pointer, 5-14 Byte address format, 5-2 Byte memory, 5-2 Byte to Integer instruction, 9-129, 10-35 C Cables order number, E-2 PC/PPI, setting parameters, 7-10 PROFIBUS network, 7-33 removing modules, 2-8 Calculating power requirements, 2-18, 2-20 Call Subroutine, with parameters, 9-146 Canadian Standards Association (CSA), A-2 CE cert
Index Compiling, errors rule violations, B-4 system response, 4-38 Configuration communications hardware, 3-2, 7-3 creating drawings, 4-4 of PC with CP card and programming device, 7-12 of PC with MPI card and programming device, 7-12 output states, 6-8 retentive ranges of memory, 5-19 Connections, MPI logical, 7-29 Connector terminal identification CPU 221 AC/DC/Relay, A-10 CPU 221 DC/DC/DC, A-10 CPU 222 AC/DC/Relay, A-15 CPU 222 DC/DC/DC, A-15 CPU 224 AC/DC/Relay, A-20 CPU 224 DC/DC/DC, A-20 EM221 Digita
Index CPU basic operation, 4-5 clearing memory, 4-29 error handling, 4-36 fatal errors, B-2 general technical specifications, A-3 going online, 3-9 hardware supported for network communications, 7-3 ID register (SMB6), C-4 memory areas, 5-2 memory ranges, G-3 modem connection, 7-25–7-30 module, 1-5 operand ranges, 8-8 password, 4-27 power requirements, 2-18 scan cycle, 4-22 selecting mode, 4-25 CPU 221 backup, 1-3 comm ports, 1-3 expansion modules, 1-3 features, 8-7 I/O, 1-3 I/O numbering example, 6-3 inpu
Index CPU 224 AC/DC/Relay connector terminal identification, A-20 order number, E-1 specifications, A-16 CPU 224 DC/DC/DC connector terminal identification, A-20 order number, E-1 specifications, A-16 CPU modules dimensions CPU 221, 2-4 CPU 222, 2-4 CPU 224, 2-5 expansion I/O modules, 2-5 screw sizes for installation, 2-4–2-6 installation procedure, panel, 2-6 procedure, removing, 2-8 screw sizes for installation, 2-4–2-6 Creating a program, example: set up timed interrupt, 4-18 Current time values, updati
Index Downloading mode requirements, 4-25 program, 5-15 EM223 24VDC Digital Combination 8 In/8 Out, order number, E-1 EN/ENO, guidelines, 4-18 Enable Interrupt instruction, 9-169 Encode instruction, 9-131 End instruction, 9-141 E ENO instructions, 9-164 Editors Environmental specifications, A-3 Function Block Diagram (FBD), 4-9 Equipment requirements Ladder Logic (LAD), 4-8 S7-200, 1-2 Statement List (STL), 4-6 STEP 7-Micro/WIN 32, 3-2 EEPROM, 5-15, 5-17 Error handling copying V memory, 5-20 fatal errors,
Index operation with Reset and Start, 9-29 operation with Reset and without Start, 9-28 I/O numbering, 6-2, 6-3 increment, 9-80, 10-23 Interrupt Routine instructions, 9-174 Invert, 9-115–9-117 Jump to Label, 9-144–9-146 Last-In-First-Out, 9-109 logic stack, 9-194–9-196 loop control (PID), 9-94–9-96 math, 9-77, 9-83, 10-21 memory fill, 9-103–9-105 move and swap, 9-102–9-104, 10-25–10-27 MPI card with master/slave, 7-4 Network Read/Network Write, 9-178–9-180 on-delay timer, 9-20, 9-21, 10-13, 10-14 output in
Index For instruction, 9-150 Force function, 4-34 Freeport mode and operation modes, 9-183 character interrupt control, 9-188 definition, 9-169 enabling, 9-183 initializing, 9-184 operation, 9-183 SMB2, freeport receive character, C-2 SMB3, freeport parity error, C-2 SMB30, SMB130 freeport control registers, 9-184, C-6 user-defined protocol, 7-30 using the PC/PPI cable, 7-35–7-36 Freeze outputs, 6-8 Function Block Diagram basic elements, 4-6 program status, 4-33 Function Block Diagram Editor, 4-9 G Gap up
Index I/O status, SMB5, C-3 IEC 1131-3 instruction set, 4-10 IEC 1131-3 variable data typing, 4-11 Immediate contact instructions, 9-3 Immediate I/O, 4-24 Increment Byte instruction, 9-78 Increment Double Word instruction, 9-79 Increment instruction, 10-22 Increment instructions Add Double Integer, 9-73 Add Integer, 9-72 example, 9-80, 10-23 Increment Byte, 9-78 Increment Double Word, 9-79 Increment Word, 9-78 Increment Word instruction, 9-78 Incrementing a pointer, 5-14 Indirect addressing, 5-13–5-15 & an
Index Compare Integer, 9-11 Compare Less Than, 10-8 Compare Less Than or Equal, 10-9 Compare Not Equal, 10-8 Compare Real, 9-13 conversion, 4-16–4-18 Count Down, 10-16 Count Up, 10-15 Count Up/Down, 10-17 counter, 9-24 Decode, 9-131 Decrement, 10-22 Decrement Byte, 9-78 Decrement Double Word, 9-79 Decrement Word, 9-78 Detach Interrupt, 9-165 Disable Interrupt, 9-169 Divide Double Integer, 9-75 Divide Integer, 9-74 Divide Integer to Double Integer, 9-76 Divide Real, 9-82 Double Integer to ASCII, 9-138 Doubl
Index Reset, 9-7 Reset Dominant Bistable, 10-6 Reset Immediate, 9-8 Return from Interrupt Routine, 9-167 Return from Subroutine, 9-145 Rotate Left Byte, 9-119 Rotate Left Double Word, 9-121 Rotate Left Word, 9-120 Rotate Right, 10-30 Rotate Right Byte, 9-119 Rotate Right Double Word, 9-121 Rotate Right Word, 9-120 Round, 9-127 Segment, 9-133 Sequence Control Relay, 9-153 Set, 10-4 Set Dominant Bistable, 10-6 Set Real-Time Clock, 9-70 Shift Left, 10-29 Shift Left Byte, 9-116 Shift Left Double Word, 9-118 Sh
Index Local I/O, addressing, 6-2 Logic Operations instructions And, 10-26 And Byte, 9-110 And Double Word, 9-112 And Word, 9-111 example And, Or, Exclusive Or, 9-113–9-115, 10-27–10-29 Invert, 9-115–9-117 Exclusive Or, 10-26 Exclusive Or Byte, 9-110 Exclusive Or Double Word, 9-112 Exclusive Or Word, 9-111 Invert Byte, 9-114 Invert Double Word, 9-114 Invert Word, 9-114 Not, 10-28 Or, 10-26 Or Byte, 9-110 Or Double Word, 9-112 Or Word, 9-111 Logic Pop instruction, 9-193–9-195 Logic Push instruction, 9-192–9-
Index Memory retention, 5-15–5-20 battery cartridge (optional), 5-15 EEPROM, 5-15, 5-17, 5-20 power-on, 5-17–5-21 ranges, 5-19 super capacitor, 5-15 Messages, token-passing network, 7-43 Micro/WIN 32 equipment requirements, 3-2 installing, 3-3 troublehsooting, 3-4 programming conventions, 8-2 Mode control, PID loops, 9-92 Mode switch, operation, 4-25 Modem 10-bit, 7-23 11-bit, 7-25 cable requirements, 7-25 network communications, 7-25–7-30 null modem adapter, 7-37, 7-40 PC/PG to CPU connection, 7-25–7-26 s
Index Multiple master network, 7-4 Multiple Master Network check box, 7-11 Multiply Double Integer instruction, 9-75 Multiply instruction, 10-20 Multiply Integer instruction, 9-74 Multiply Integer to Double Integer instruction, 9-76 Multiply Real instruction, 9-82 N Negative Transition instruction, 9-4, 10-3 Network biasing, 7-32 cable specifications, 7-33 communication port, 7-31 communications setup, 7-2–7-19 components, 7-31 connectors, 7-32 device address, 7-28 gap update factor (GUF), 7-41 highest st
Index Parameter set, module MPI Card (PPI), 7-14 PC/PPI Cable (PPI), 7-10–7-11 selecting, 7-9–7-10 Password clearing, 4-29 CPU, 4-27 configuring, 4-28 lost, 4-29 privilege level, 4-27 restricting access, 4-27 PC/PPI cable baud rate switch selections, 7-35, A-30 connection procedure, 3-5, 7-38 DIP switch settings, 3-5, 7-38 pin outs, A-31 setting up parameters, 7-10 specifications, A-30 using with a modem, 7-25–7-26, 7-37, 7-40 using with the Freeport communication mode, 7-35–7-36 Peer-to-peer communication
Index Program analog inputs, 4-22 basic elements, 4-18 debugging, 4-30–4-32 downloading, 5-15 executing, 4-23 inputs/outputs, 4-5 monitoring, 4-30–4-32 monitoring status, 4-32, 4-33 restoring from memory cartridge, 5-24 saving permanently, 5-20 storage, 5-15–5-18, 5-22 structure, 4-18 uploading, 5-15 using Status/Force Chart, 4-31 using subroutines, 9-145 Program Control instructions Call, example, 9-149–9-151 End, 9-141 example, 9-143–9-145 ENO, 9-164 For, 9-150 For/Next, example, 9-152–9-154 Jump to Labe
Index Removing, terminal block connector, 2-12 Repeater, order number, E-2 Repeaters, PROFIBUS network, 7-34 Reset Dominant Bistable instruction, 10-6 Reset Immediate instruction, 9-8 Reset instruction, 9-7, 10-4 Resistor/capacitor networks, relay applications, 2-17 Resources dialog box for Windows NT, 7-8 Restarting the CPU, after a fatal error, 4-37 Retaining memory, 5-15–5-20 Retentive ranges of memory, defining, 5-19 Return from Interrupt Routine instruction, 9-167 Return from Subroutine instruction, 9
Index Setting up communications, 7-2–7-19 communications parameters, 7-4 Shift instructions example of shift and rotate, 9-122–9-124, 10-31–10-33 example of shift register bit, 9-125–9-127 Shift Left, 10-29 Shift Left Byte, 9-116 Shift Left Double Word, 9-118 Shift Left Word, 9-117 Shift Register Bit, 9-123 Shift Right, 10-29 Shift Right Byte, 9-116 Shift Right Double Word, 9-118 Shift Right Word, 9-117 Shift Left Byte instruction, 9-116 Shift Left Double Word instruction, 9-118 Shift Left instruction, 10-
Index Standard contact instructions, 9-2, 10-2 Standard rail clearance requirements, 2-3–2-5 dimensions, 2-4 high-vibration installations, 2-7 installation procedure, 2-7 removal procedure, 2-8 using DIN rail stops, 2-7 vertical installations, 2-7 Standards, national and international, A-2 Statement list, 4-6 Statement List Editor, 4-6 Status bits (SMB0), C-1 Status byte, High-Speed Counter, 9-39 Status/Force Chart and scan cycle, 4-34 modifying program, 4-31 STEP 7-Micro/WIN 32, iv equipment requirements,
Index Transmit instruction, 9-182, 9-184 example, 9-189 Troubleshooting compile errors, B-4 error handling, 4-36 fatal errors, 4-37, B-2 Micro/WIN 32 installation, 3-4 network read/network write errors, 9-176 non-fatal errors, 4-38 password lost, 4-29 PID loop, 9-93 run-time programming errors, B-3 S7-200, D-1 Truncate instruction, 9-127, 10-32 U Uploading, program, 5-15 User-defined protocol, Freeport mode of communication, 7-30 Using pointers, 5-13 & and *, 5-13 modifying a pointer, 5-14 Using subroutin
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