Specifications

SIMATIC Instructions
9-27
S7-200 Programmable Controller System Manual
C79000-G7076-C233-01
9.5 SIMATIC High-Speed Counter Instructions
High-Speed Counter Definition, High-Speed Counter
The High-Speed Counter Definition instruction assigns
a MODE to the referenced high-speed counter (HSC).
See Table 9-5.
The High-Speed Counter instruction, when executed,
configures and controls the operational mode of the
high-speed counter, based on the state of the HSC
special memory bits. The parameter N specifies the
high-speed counter number.
CPU 221 and CPU 222 do not support HSC1 and HSC2.
Only one HDEF box may be used per counter.
HDEF: Error conditions that set ENO = 0:
SM4.3 (run-time), 0003 (input point conflict), 0004 (illegal
instruction in interrupt), 000A (HSC redefinition)
HSC: Error conditions that set ENO = 0:
SM4.3 (run-time), 0001 (HSC before HDEF), 0005
(simultaneous HSC/PLS)
Inputs/Outputs Operands Data Types
HSC Constant BYTE
MODE Constant BYTE
N Constant WORD
Understanding the High-Speed Counter Instructions
High-speed counters count high-speed events that cannot be controlled at CPU
scan rates, and can be configured for up to twelve different modes of operation.
The counter modes are listed in Table 9-5. The maximum counting frequency of a
high-speed counter is dependent upon your CPU type. See Appendix A for more
information about your CPU.
Each counter has dedicated inputs for clocks, direction control, reset, and start,
where these functions are supported. For the two-phase counters, both clocks may
run at their maximum rates. In quadrature modes, an option is provided to select
one times (1x) or four times (4x) the maximum counting rates. All counters run at
maximum rates without interfering with one another.
L
A
D
S
T
L
HDEF HSC, MODE
HSC N
HDEF
EN
HSC
MODE
HSC
EN
N
ENO
ENO
222 224
333
221