Specifications

SIMATIC Instructions
9-125
S7-200 Programmable Controller System Manual
C79000-G7076-C233-01
Shift Register Bit Example
LAD STL
LD I0.2
EU
SHRB I0.3, V100.0, 4
I0.2
SHRB
DATAI0.3
P
S_BITV100.0
N
4
I0.2
Timing Diagram
I0.3
7
1
V100
MSB LSB
S_BIT
I0.3
010
0
Overflow (SM1.1)
x
1
V100
S_BIT
I0.3
101
Overflow (SM1.1)
0
0
V100
S_BIT
I0.3
110
Overflow (SM1.1)
1
First shift Second shift
Before first shift
After first shift
After second shift
Positive transition (P)
FBD
SHRB
EN
DATA
I0.3
S_BIT
V100.0
N4
ENO
ENO
EN
OUTINI0.2
P
Figure 9-41 Example of Bit Shift Register Instruction for LAD, STL, and FBD