Specifications

SIMATIC Instructions
9-172
S7-200 Programmable Controller System Manual
C79000-G7076-C233-01
Understanding the Interrupt Priority and Queuing
Interrupts are prioritized according to the fixed priority scheme shown below:
 Communication (highest priority)
 I/O interrupts
 Time-based interrupts (lowest priority)
Interrupts are serviced by the CPU on a first-come-first-served basis within their
respective priority assignments. Only one user-interrupt routine is ever being
executed at any point in time. Once the execution of an interrupt routine begins,
the routine is executed to completion. It cannot be pre-empted by another interrupt
routine, even by a higher priority routine. Interrupts that occur while another
interrupt is being processed are queued for later processing.
The three interrupt queues and the maximum number of interrupts they can store
are shown in Table 9-22.
Table 9-22 Interrupt Queues and Maximum Number of Entries per Queue
Queue
CPU 221 CPU 222 CPU 224
Communications queue 4 4 4
I/O Interrupt queue 16 16 16
Timed Interrupt queue 8 8 8
Potentially, more interrupts can occur than the queue can hold. Therefore, queue
overflow memory bits (identifying the type of interrupt events that have been lost)
are maintained by the system. The interrupt queue overflow bits are shown in
Table 9-23. You should use these bits only in an interrupt routine because they are
reset when the queue is emptied, and control is returned to the main program.
Table 9-23 Special Memory Bit Definitions for Interrupt Queue Overflow Bits
Description (0 = no overflow, 1 = overflow)
SM Bit
Communication interrupt queue overflow SM4.0
I/O interrupt queue overflow SM4.1
Timed interrupt queue overflow SM4.2