Technical data

Table Of Contents
System Status Lists (SSL)
System Software for S7-300/400 System and Standard Functions - Volume 2/2
33-44
A5E00739858-01
Data Record
A data record of partial list ID W#16#xy90 has the following structure:
Name Length Meaning
dp_m_id 1 byte DP master system ID
rack_dp_m 1 byte Rack number of the DP master
with a standard CPU: 0
with a H system: 0 or 1
Steckpl_dp_m 1 byte Slot of the DP master or
slot of the CPU (with integrated DP interface)
Subm_dp_m 1 byte with integrated DP interface: interface number of the
DP master:
-
1: X2
-
2: X1
-
3: IF1
-
4: IF2
with external DP interface: 0
Logadr 1 word logic start address of the DP master
dp_m_sys_cpu 1 word reserved
dp_m_sys_dpm 1 word reserved
dp_m_state 1 byte further properties of the DP master system
Bit 0: DP mode
0: S7 compatible
1: DPV1
Bit 1 DP cycle
0: not equidistant
1: equidistant
Bit 2 to 6: Reserved
Bit 7: DP master type
0: integrated DP master
1: external DP master
Reserve 3 bytes Reserved
Note on multicomputing (S7-400 only)
All the partial lists only supply information on modules which are assigned to a
CPU. In multicomputing mode you must therefore sample all CPUs in order to
obtain the data of all connected modules.