Technical data

Table Of Contents
System Status Lists (SSL)
System Software for S7-300/400 System and Standard Functions - Volume 2/2
33-58
A5E00739858-01
Data record
A data record of the partial list with the ID W#16#xy95 is structured as follows:
Name Length Meaning
dp_m_id 1 byte DP master system ID/PROFINET IO system ID
rack_dp_m 1 byte Module rack number of the DP master
For standard CPU: 0
For H system: 0 or 1
steckpl_dp_m 1 byte Slot of the DP master or
slot of the CPU (with integrated DP interface)
subm_dp_m 1 byte with integrated DP interface: Interface ID of the DP master:
-
1: X2
-
2: X1
-
3: IF1
-
4: IF2
with external DP interface: 0
logadr 2 bytes Logical start address of the DP master
dp_m_sys_cpu 2 bytes Reserved
dp_m_sys_dpm 2 bytes Reserved
dp_m_state 1 bytes Further properties of the DP master system
Bit 0: DP mode
0: S7 compatible
1: DPV1
Bit 1: DP cycle
0: not equidistant
1: equidistant
Bit 2 to 6: Reserved
Bit 7: Type of DP master
0: integrated DP master
1: external DP master
dp_address 1 byte DP node number (PROFIBUS address)
reserve 2 bytes Reserved
tsal_ob 1 byte Assigned clock synchronization interrupt OB (only relevant if the DP
cycle is equidistant)
reserve 1 byte Reserved
baudrate 4 bytes Transmission rate of the DP master system (hex value)
dp_iso_takt 4 bytes Period of the equidistant DP cycle in ìs
reserve 16 bytes Reserved
Information on Multicomputing (only S7-400)
All the partial lists only supply information on the modules which are assigned to a
CPU. In multicomputing mode you must therefore sample all the CPUs in order to
obtain the data of all the connected modules.