AirPrime IoT Module Technical Specification Rev9 0
Table Of Contents
- Contents
- List of Figures
- List of Tables
- 1. Introduction
- 2. Pad Definition
- 3. Detailed Interface Specifications
- 3.1. Power Supply
- 3.2. Current Consumption
- 3.3. VGPIO
- 3.4. BAT_RTC
- 3.5. SIM Interface
- 3.6. USB
- 3.7. Electrical Information for Digital I/O
- 3.8. General Purpose Input/Output (GPIO)
- 3.9. Main Serial Link (UART1)
- 3.10. POWER-ON Signal (PWR_ON_N)
- 3.11. Reset Signal (RESET_IN_N)
- 3.12. Clock Interface
- 3.13. Debug Interfaces
- 3.14. RF Interface
- 4. Mechanical Drawings
- 5. Design Guidelines
- 6. Reliability Specification
- 7. FCC Legal Information
- 8. Ordering Information
- 9. Terms and Abbreviations
4115834 Rev 9.0 August 28, 2017 12
Product Technical Specification
Introduction
Feature
Description
Connectivity
• Multiple (up to 20) cellular packet data profiles
• Sleep mode for minimum idle power draw
• Mobile-originated PDP context activation / deactivation
• Support QoS profile
▪ Release 97 – Precedence Class, Reliability Class, Delay Class, Peak
Throughput, Mean Throughput
▪ Release 99 QoS negotiation – Background, Interactive, and
Streaming
• Static and Dynamic IP address. The network may assign a fixed IP
address or dynamically assign one using DHCP (Dynamic Host
Configuration Protocol).
• Supports PAP and CHAP authentication protocols
• PDP context type (IPv4, IPv6, IPv4v6). IP Packet Data Protocol context
• RFC1144 TCP/IP header compression
Environmental
Operating temperature ranges (industrial grade):
• Class A: -30°C to +70°C
• Class B: -40°C to +85°C
RTC
Real Time Clock (RTC) with calendar
1.4. Architecture
The figure below presents an overview of the AirPrime HL7518 internal architecture and external
interfaces.
AirPrime HL7518
Memory
(Flash + RAM)
SAW
Filters
26MHz
32.768KHz
UART1 (8 pins)
Trace Debug (5 pins)
VBATT
GND
VGPIO
BAT_RTC
GPIO x 14
RESET_IN
JTAG
LGA-
146
Baseband
SIM1
MCU DSP
PMU RF
Analog Baseband
Peripherals
LGA-
146
32K_CLKOUT
PWR_ON
Dulpexer
PA
USB
Antenna
Switch
Antenna
Switch
Figure 1. Architecture Overview