WM_ Wireless CPU Q24 Series Product Technical Specification Revision: 003 Date: November 2006
Wireless CPU Q24 Series Product Technical Specification Reference: WM_PRJ_Q24NG_PTS_001 Revision: 003 Date: November 2006 Powered by the Open AT® Software Suite confidential © Page: 1 / 81 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Wireless CPU Q24 Series Cautions This platform contains a modular transmitter. This device is used for wireless applications. Note that all electronics parts and elements are ESD sensitive. Information provided herein by WAVECOM is accurate and reliable. However, no responsibility is assumed for its use and any of such WAVECOM information is herein provided "as is" without any warranty of any kind, whether express or implied.
Wireless CPU Q24 Series Web Site Support General information about Wavecom and its range of products: www.wavecom.com Specific support is available for the Q24 Classic, Plus, Extended and Auto Wireless CPU: www.wavecom.com/Q24Classic, www.wavecom.com/Q24Plus, www.wavecom.com/Q24Extended, www.wavecom.com/Q24Auto Carrier/Operator approvals: www.wavecom.com/approvals Open AT® Introduction: www.wavecom.com/OpenAT Developer support for software and hardware: www.wavecom.
Wireless CPU Q24 Series Overview This Product Specification document defines and specifies the Wireless CPU Q24 Series is available in four different GSM/GPRS Class 10 quad-band versions: • Q24 Classic: EGSM 900/1800/850/1900 MHz version with 32 Mb of Flash memory and 16 Mb of PSRAM (32/16), T° range [-20°C / +55°C]. • Q24 Plus: EGSM/GPRS 900/1800/850/1900 MHz version with 32 Mb of Flash memory and 16 Mb of PSRAM (32/16), T° range [-20°C / +55°C].
Wireless CPU Q24 Series Document History Revision Date List of revisions 001 May 2006 Creation (Preliminary version) 002 September 2006 First update 003 November 2006 Update confidential © Page: 5 / 81 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Wireless CPU Q24 Series Contents 1 References.......................................................................................................10 1.1 Reference Documents ..................................................................................... 10 1.1.1 Wavecom Reference Documents............................................................. 10 1.1.2 General Reference Documents ................................................................ 10 1.2 Abbreviations............................
Wireless CPU Q24 Series 3.10 Activity Status Indication ................................................................................ 37 3.11 Analog to Digital Converter (ADC) ................................................................... 38 3.12 Audio Interface ............................................................................................... 38 3.12.1 Microphone Inputs.................................................................................. 39 3.12.2 Speaker Outputs .........
Wireless CPU Q24 Series 6.5 6.6 6.7 7 Antenna Cable ................................................................................................ 73 RF board-to-board Connector.......................................................................... 74 GSM Antenna ................................................................................................. 74 Appendix.........................................................................................................75 7.
Wireless CPU Q24 Series Table of Figures Figure 1: Functional architecture .............................................................................. 17 Figure 2: Power supply during burst emission.......................................................... 21 Figure 3: Maximum voltage ripple (Uripp) versus Frequencies in GSM & DCS.......... 23 Figure 4: UART1 Serial Link signals .......................................................................... 31 Figure 5: UART2 Serial Link signals ............
Wireless CPU Q24 Series References 1 References 1.1 Reference Documents For more details, several reference documents may be consulted. The Wavecom reference documents are provided in the Wavecom documents package contrary to the general reference documents, which are not Wavecom owned. 1.1.
Wireless CPU Q24 Series References 1.
Wireless CPU Q24 Series References Abbreviation Description IF Intermediate Frequency INTR INTeRrupt I/O Input / Output LCD Liquid Crystal Display LED Light Emitting Diode LNA Low Noise Amplifier LSB Less Significant Bit MAX MAXimum MIC MICrophone MIN MINimum MMS Multimedia Message Service MS Mobile Station NOM NOMinal NTC Negative Temperature Coefficient PA Power Amplifier PBB PolyBrominated Biphenyl PBDE PolyBrominated Diphenyl Ethers PCB Printed Circuit Board PCL Power
Wireless CPU Q24 Series References Abbreviation Description SRAM Static RAM TDMA Time Division Multiple Access TU Typical Urban fading profile TUHigh Typical Urban, High speed fading profile TDMA Time Division Multiple Access TX Transmit TYP TYPical UART Universal Asynchronous Receiver-Transmitter VLSI Very Large Scale Integration VSWR Voltage Standing Wave Ratio ©Confidential Page: 13 / 81 This document is the sole and exclusive property of WAVECOM.
Wireless CPU Q24 Series General Description 2 General Description 2.1 General Information The Wireless CPU Q24 Series are self-contained EGSM/GPRS 900/1800 and 850/1900 quad-band Wireless CPUs with the following characteristics: Note: The Q24 classic is limited to GSM only (GPRS not supported). 2.1.1 Overall Dimensions Completely shielded: • Length: 58.4 mm • Width: 32.2 mm • Thickness: 3.
Wireless CPU Q24 Series General Description The Wireless CPU Q24 Series are designed to integrate various types of specific process applications such as vertical applications (telemetry, multimedia, automotive). The Open AT firmware offers a set of AT commands to control the Wireless CPU. With this standard Operating System, some interfaces of the Wireless CPU are not available since they are dependent on the peripheral devices connected to the Wireless CPU.
Wireless CPU Q24 Series General Description 2.1.5 External RF Connection Interfaces The Wireless CPU Q24 Series are available with different external RF connection configurations: Product reference UFL UFL or MMS Antenna pad IMP Position Bottom side Top side Top side Bottom side Q24 Classic X X X Q24 Plus X X X Q24 Extended X X X X X Q24 Automotive X 2.1.
Wireless CPU Q24 Series General Description 2.
Wireless CPU Q24 Series General Description 2.2.1 RF Functionalities The Radio Frequency (RF) range complies with the Phase II EGSM 900/DCS 1800 and GSM 850/PCS 1900 recommendations. The frequencies are given below: GSM band Transmit band (Tx) GSM 850 EGSM 900 DCS 1800 PCS 1900 824 880 1710 1850 to to to to 849 MHz 915 MHz 1785 MHz 1910 MHz Receive band (Rx) 869 925 1805 1930 to to to to 894 MHz 960 MHz 1880 MHz 1990 MHz The Radio Frequency (RF) part is based on a specific quad-band chip.
Wireless CPU Q24 Series Interfaces 3 Interfaces Note: Some of the Wireless CPU Q24 Series interface signals are multiplexed in order to limit the total number of pins. But this architecture imposes some restrictions. Example: If the SPI bus and 2-wire bus are multiplexed and if the SPI bus is used, then the 2wire bus is not available. Caution: To power-ON the Wireless CPU Q24 Series correctly and to avoid any damage, all external signals must be inactive when the Wireless CPU Q24 Series is OFF. 3.
Wireless CPU Q24 Series Interfaces The available interfaces on the GPC are shown below: OS 6.57 Section Name 3.4 3.5 3.6 3.7 3.8 3.9 Serial interface Keyboard Interface Main Serial Link Auxiliary Serial Link SIM interface General Purpose IO Activity status indication Analog to digital converter Audio Interface Battery charging interface ON/~OFF Boot Reset External interrupt VCC output Real Time Clock RF interface 3.10 3.11 3.12 3.14 3.15 3.16 3.17 3.18 3.
Wireless CPU Q24 Series Interfaces VBATTT Uripp Uripp t = 577 μs T = 4,615 ms Figure 2: Power supply during burst emission Two different inputs are provided for the power supply: • VBATT is used to supply the RF part and • VDD is used to supply the baseband part. VBATT: Directly supplies the RF components with 3.6 V. It is essential to keep a minimum voltage ripple at this connection in order to avoid any phase error. In particular, VBATT supplies the RF Power Amplifier.
Wireless CPU Q24 Series Interfaces Electrical characteristics Signal MIN NOM MAX VBATT 3.2 V 3.6 V 4.5 V * VDD 3.1 V 4.5 V *Max operating Voltage Standing Wave Ratio (VSWR) 2:1. 3.2.2 Power Supply Recommendation The VBATT voltage limits must be considered at any time. The worst condition is during the burst period transmission, when current consumption is at its highest. During this period, the VBATT voltage is minimum: • The output voltage of the power supply drops.
Wireless CPU Q24 Series Interfaces Uripp Max (mVpp) Freq. (kHz) Uripp Max (mVpp) <100 200 300 400 500 600 700 50 15.5 6.8 3.9 4 2 8.2 800 900 1000 1100 1200 1300 1400 4 15.2 9.5 32 22 29 30 Uripp (mVpp) Freq. (kHz) 50 45 40 35 30 25 20 15 10 5 0 200 400 600 800 1000 1200 Freq.
Wireless CPU Q24 Series Interfaces 3.2.3 Power Consumption The Wireless CPU Q24 Series support different power consumption modes: Working modes Comments OFF mode ALARM mode The Wireless CPU is in OFF mode. The Wireless CPU is in OFF mode with RTC block running, when an ALARM occurs, the Wireless CPU wakes-up automatically. The Wireless CPU is synchronized with an RF GSM/GPRS network. The internal 26 MHz of the Wireless CPU is constantly active. The Wireless CPU is synchronized with an RF GSM/GPRS tester.
Wireless CPU Q24 Series Interfaces • No processing is required by the Open AT® application. INOM IMAX IMAX Unit average average peak Operating mode Parameters OFF Mode VBATT= 3.6V 16.5 18 μA Alarm Mode VBATT= 3.6V 18.5 20 μA Paging 9 10.5 11 150Rx mA Paging 2 13 13.5 150Rx mA Paging 9 2.8 3 150Rx mA Paging 2 5.5 5.8 150Rx mA Fast Standby VBATT = 3.6V 9.5 11 - mA Slow Standby VBATT = 3.6V 1.
Wireless CPU Q24 Series Interfaces INOM IMAX IMAX Unit average average peak Operating mode Parameters OFF Mode VBATT = 3.6V 16.5 18 μA Alarm Mode VBATT = 3.6V 18.5 20 μA Paging 9 10.5 11 150Rx mA Paging 2 13 13.5 150Rx mA Paging 9 N/A N/A N/A mA Paging 2 N/A N/A N/A mA Fast Standby VBATT = 3.6V 9.5 11 Slow Standby VBATT = 3.6V N/A N/A Fast Idle Mode Slow Idle Mode Connected Mode Transfer Mode Class 8 (4Rx/1Tx) GPRS Transfer Mode Class 10 (3Rx/2Tx) 3.2.3.
Wireless CPU Q24 Series Interfaces The following waveform shows only the current form versus time: Current Waveform Connected mode with One TX burst at PCL5 and one RX burst Slow idle mode paging 9 GPRS Class 10 Transfer mode with two TX bursts at PCL5 and three RX burst Fast idle mode paging 9 ©Confidential Page: 27 / 81 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Wireless CPU Q24 Series Interfaces 3.3 Electrical Information for Digital I/O All digital I/O comply with a 3 volt CMOS. Electrical characteristics Parameter I/O type min Max Conditions VIL CMOS -0.5 V 0.8 V VIH CMOS 2.1 V 3.0 V VOL 1X -0.2V 0.2 V IOL = -1 mA - 2X -0.2V 0.2 V IOL = -2 mA - 3X -0.2V 0.2 V IOL = -3 mA VOH 1X 2.55 V 2.95V IOH = 1 mA - 2X 2.55 V 2.95V IOH = 2 mA - 3X 2.55 V 2.95V IOH = 3 mA 3.4 Serial Interface 3.4.
Wireless CPU Q24 Series Interfaces Pin description Signal Pin I/O SPI_CLK 10 SPI_IO O 8 I/O type Reset state Description CMOS 1X (C5) Pull-up to 2V8 SPI Serial Clock SCL Pull-up to 2V8 SPI Data SDA 2V8 SPI Aux. Enable GPO0 I/O CMOS / CMOS 1X (C2) SPI_AUX 26 O CMOS 1X (C3) Multiplexed with (C2), (C3) and (C5): To obtain more details on I/O type, refer to chapter "I/O Circuit diagram" 3.4.
Wireless CPU Q24 Series Interfaces An AT command or open AT API allows the input key code to be obtained (see the AT+CMER command description). This code must then be processed by the application. For a total of 25 keys (5 rows x 5 columns), the keyboard interface provides 10 connections: • 5 rows (ROW0 to ROW4) and • 5 columns (COL0 to COL4) The scanning is digital, and the debouncing is performed in the Wireless CPU. No discrete components such as R, C (Resistor, Capacitor) are needed.
Wireless CPU Q24 Series Interfaces The two additional signals are: • Data Carrier Detect (CT109/DCD). • Ring Indicator (CT125/RI).
Wireless CPU Q24 Series Interfaces 3.7 Auxiliary Serial Link (UART2) For specific applications, an auxiliary serial interface (UART2) is available on the Wireless CPU Q24 Series. E.g. Bluetooth connectivity: See AT commands interface guide (Bluetooth) [5].
Wireless CPU Q24 Series Interfaces Pin description Signal Pin I/O I/O type Reset state Description SIM_CLK 3 O 2V9/1V8 0V SIM Clock SIM_RST 5 O 2V9/1V8 0V SIM Reset SIM_DATA 7 I/O 2V9/1V8 0V SIM Data SIM_VCC 9 O 2V9/1V8 0V SIM Power Supply SIM_PRES 50 I 2V8 High impedance SIM Card Detect Caution: Disturbances (digital noise, ESD) in the SIM signals may interrupt the Wireless CPU functionality, a good layout of these signals are recommended: • Ground separation between SI
Wireless CPU Q24 Series Interfaces 3.8.2 SIM Card Holder An optional SIM Card holder may be placed on top of Wireless CPU. This SIM Card holder does not use the SIM_PRES signal. Caution: Customers are advised to verify that the SIM Card environmental specification used is compliant with the Wireless CPU Q24NG environmental specifications [3] (see the Wireless CPU Q24NG Product Technical Specification WM_PRJ_Q24NG_PTS_001).
Wireless CPU Q24 Series Interfaces 3.9 General Purpose Input/Output The Wireless CPU Q24 Series provide: • 6 General Purpose I/O, • 4 General Purpose Output, • 1 General Purpose Input. They are used to control any external devices such as an LCD or a Keyboard backlight.
Wireless CPU Q24 Series Interfaces Pin description Signal Pin I/O I/O type Reset state Description Multiplexed with GPIO2 54 I/O CMOS / 2X (C1) High impedance General Purpose I/O CT125/RI1 GPIO3 51 I/O CMOS / 2X (C1) High impedance General Purpose I/O CT109/DCD1 (C1): To obtain more details on I/O type, refer to chapter "I/O Circuit diagram" 3.10 Activity Status Indication The activity status indication signal may be used to drive a FLASH LED through an open collector transistor.
Wireless CPU Q24 Series Interfaces 3.11 Analog to Digital Converter (ADC) Equivalent circuit Q24 Series AUXV0 An Analog to Digital Converter is provided by the Wireless CPU Q24 Series. This converter is a10-bit resolution, ranging from 0 to 2.8 V.
Wireless CPU Q24 Series Interfaces Caution: When speakers and microphones are exposed to the external environment, it is recommended to add ESD protection on the audio interface lines. 3.12.1 Microphone Inputs The MIC2 inputs already include the biasing for an electret microphone, thus allowing easy connection to a handset. The MIC1 inputs do not include an internal bias. MIC1/SPK1 may be used for a hands-free system or a handset, including biasing circuit for the microphone.
Wireless CPU Q24 Series Interfaces Microphone gain versus Max input voltage Using Controller 1 Transmit Gain (dB) Using Controller 2 Max Vin (mVrms) Transmit Gain (dB) Max Vin (mVrms) +30 43.80 -6.5 3031 +33 31.01 -6 2861 +36 21.95 0 1434 +39 15.54 +9.5 480 +42 11 +10 454 +45 7.79 +30.3 43.80 +48 5.51 +30.8 41.36 +51 3.9 +50.8 4.14 - - +51.3 3.90 * For more details, refer to the AT commands documentation [5] 3.12.1.
Wireless CPU Q24 Series Interfaces Pin description Signal Pin I/O I/O type MIC1P 42 I Analog MIC1N 44 I Analog Description Microphone 1 positive input Microphone 1 negative input Electrical Characteristics MIC1 Electrical characteristics Parameters DC Characteristics AC Characteristics 100 Hz
Wireless CPU Q24 Series Interfaces Electrical Characteristics MIC2 Electrical characteristics Parameters Internal biasing DC Characteristics AC Characteristics 100 Hz
Wireless CPU Q24 Series Interfaces Speaker gain versus Max output voltage Receive Gain (dB)* Max output level (Vrms) Max.speaker load (Ω) +2 1.74 150 0 1.38 50 -2 1.099 32 -4 0.873 32 -6 0.693 32 -8 0.551 32 -10 0.437 32 -12 0.347 32 -14 0.276 32 -16 0.219 32 -18 0.174 32 -20 0.138 32 -22 0.110 32 -24 0.087 32 -26 0.069 32 *Analog gain: may not be significant 3.12.2.
Wireless CPU Q24 Series Interfaces 3.13 Buzzer Output 3.13.1 Hardware Description The buzzer interface is accessible through an open drain embedded on the Wireless CPU Q24 Series. A buzzer may be directly connected between this output and VBATT. Equivalent circuit Q24 Series Pin description Signal Pin I/O I/O type Description BUZZER 49 O Analog Buzzer output Operating conditions Parameter Condition VOL IPEAK Max Unit Iol = 100mA 0.
Wireless CPU Q24 Series Interfaces Caution: A diode against transient peak voltage must be connected as described below. Figure 7: Buzzer connection For the implementation of the buzzer interface, refer to the Customer Design Guidelines [3]. 3.14 Battery Charging Interface 3.14.1 Hardware Description Caution: The battery charging interface does not allow the Wireless CPU to be supplied and is only used to charge a battery connected to VBATT.
Wireless CPU Q24 Series Interfaces The Wireless CPU Q24 Series supports three types of battery technologies: • Ni-Cd (Nickel-Cadmium), which is charged with the algorithm 0 • Ni-Mh (Nickel-Métal Hydrure), which is charged with the algorithm 0 • Li-Ion (Lithium-Ion), which is charged with the algorithm 1 The algorithm controls the frequency and the connected time of switching transistor (T).
Wireless CPU Q24 Series Interfaces Pin description Signal Pin number I/O I/O type Description CHG_IN 1, 2, 4 I Analog Current source input BAT_TEMP 38 I Analog A/D converter Electrical Characteristics Parameter BAT_TEM P Min Typ Ma x Unit Resolution 10 bits Sampling rate 90.3 Ksps/s Input Impedance (R) 1M Input Impedance (C) Input signal range CHG_IN 0
Wireless CPU Q24 Series Interfaces The main parameters to be tuned are: Parameters related to time: • TPulseInCharge: Monitoring time of the VBATT voltage during a charging process (T2) • TPulseOutCharge: Monitoring time of the VBATT voltage when charging process is not activated(T3) Parameters related to voltage: • • BattLevelMin: Minimum VBATT voltage allowed by the battery (>3.2V) BattLevelMax: Maximum VBATT voltage allowed by the battery (<4.
Wireless CPU Q24 Series Interfaces Note: A charger is connected to the CHG_IN pin of the Wireless CPU. Switching transistor: Closed T2 T1 T1 T1 T2 T3 T2 T3 Time Open VBATT=BattLevelMax: Charging process ended VBAT T BattLevelMax VBATT=BattLevelMin: Charging process automatically started BattLevelMin Time Figure 8: Ni-Cd / Ni-Mh charging waveform 3.14.
Wireless CPU Q24 Series Interfaces Parameters related to safety: These parameters are important; as they ensure that the battery will not be damaged.
Wireless CPU Q24 Series Interfaces Li-Ion charging process Charger connected: CHG_IN =VBATT+0.
Wireless CPU Q24 Series Interfaces Switching transistor state 1s 1s 1s 1s 1s Close d 1s 1s 10 T3 T3 1s 1s 1s 1s Time Open When VBATT=BattLevelMin, the fast charging mode is automatically started Li-Ion charging optimization method VBATT BattLevelMax DedicatedVoltStart BattLevelMin =BattLevelM ax Pulse charging The opening time of the switching mode transistor increases until it reaches 10s, then the charging process is ended The charge of the battery is
Wireless CPU Q24 Series Interfaces To switch OFF the Wireless CPU, the pin ON/~OFF must be released and, through the firmware, the Wireless CPU may be switched OFF (using the AT+CPOF command). Equivalent circuit Q24 Series VDD 100K ON/∼OFF 47K 47K GND Pin description Signal ON/∼OFF Pin I/O I/O type 6 I CMOS Description Power ON/OFF Electrical Characteristics Parameters 3.15.2 Min Max Unit VIL 0 0.6 V VIH 2.4 5 V Operating Sequences 3.15.2.
Wireless CPU Q24 Series Interfaces Once initialization is completed (timing is SIM and network dependent) the AT interface answers "OK" to the application 1. For further details, please refer to the AT commands documentation (AT+WIND, AT+WAIP). VDD 1s minimum ON/~OFF Internal RESET Status: 240ms Typ OFF mode Reset mode AT command: ON mode Ready “AT” is send “OK” is received SIM and network dependent Figure 10: Power-ON sequence diagram 3.15.2.
Wireless CPU Q24 Series Interfaces “OK” answer AT+CPOF VDD Network dependent ON/~OFF Status: Ready OFF mode Figure 11: Power-OFF sequence diagram Caution: It is not allowed to power-OFF the Wireless CPU by disconnecting the supply pins VBATT and VDD. Note: Instead of sending AT+CPOF, use the Wireless CPU external interrupt pin (see the External interrupt) 3.16 BOOT (optional) This input may be used to download software to the Flash memory of the Wireless CPU.
Wireless CPU Q24 Series Interfaces Pin description Signal Pin I/O I/O type Reset state Description BOOT 12 I CMOS (C5) Pull-up to 2V8 Flash Downloading (C5): To obtain more details on I/O type, refer to the chapter "I/O Circuit diagram" 3.17 Reset Signal (~RST) 3.17.1 General Description The reset signal is used to force a reset procedure by providing low level, for at least 500 μs. The Wireless CPU remains in reset mode as long as the ~RST signal is held low.
Wireless CPU Q24 Series Interfaces Equivalent circuit Q24 Series Power ON Reset GND 4K7 2V8 ~RST 4K7 10nF GND VT+ System VT- Reset 10nF GND Pin description Signal Pin number I/O I/O type Description ∼RST 14 I/O Schmitt Reset Electrical characteristics Parameters Min Max VT- 0.9 1 VT+ 1.7 1.8 Reset state 0 0.4 IOL = -50 μA Normal mode 2.74 2.86 IOH = 50 μA Hysteresis thresholds ∼RST Condition This signal may also be used to provide a reset to an external device.
Wireless CPU Q24 Series Interfaces If used (as an emergency reset), it must be driven either by an open collector or an ~RST open drain output: External reset GND Figure 12: RST pin connection For the implementation of the reset interface, refer to the Customer Design Guidelines 3.17.2 Reset Sequence To activate the "emergency "reset sequence, the ~RST signal must be set to low for 500 μs minimum. As soon as the reset is completed, the AT interface answers "OK" to the application.
Wireless CPU Q24 Series Interfaces Pin description Signal Pin number I/O ~INTR 16 I I/O type Reset state Description CMOS (C5) Pull-up to 2V8 External Interrupt (C5): To obtain more details on I/O type, refer to the chapter "I/O Circuit diagram" Electrical characteristics Parameter Min Max Unit VIL -0.5 0.7 V VIH 2.2 3.0 V The external interrupt may be used to switch OFF the Wireless CPU.
Wireless CPU Q24 Series Interfaces 3.20 Real Time Clock Supply (VCC_RTC) The VCC_RTC input is used to provide a back-up power supply for the internal Real Time Clock (RTC). The RTC is supported by the Wireless CPU when power-ON, but a back-up power supply is necessary to save date and time information, when the Wireless CPU is switched off. If the RTC is not used, this pin may be left open. Equivalent circuit Q24 Series VDD>2.6V RTC regulator BAT-RTC RTC block If VDD<2.
Wireless CPU Q24 Series Interfaces 3.21 RF Interface The impedance is 50Ω nominal and the DC impedance is 0Ω. 3.21.1 RF Connections The RF interface supports 4 type of connections: • U.FL Connector (on both sides) A wide variety of cables fitted with U.FL connectors are proposed by different suppliers. • MMS Connector The MMS connector stands on three pliable legs. The design guarantees the receptacle stability after placement.
Wireless CPU Q24 Series Interfaces 3.21.2 RF Performance RF performance is compliant with the ETSI recommendation ETSI TS 151 010-1.
Wireless CPU Q24 Series Technical Specifications 4 Technical Specifications 4.
Wireless CPU Q24 Series Technical Specifications Pin Name I/O I/O type Reset state Description Dealing with unused pins CMOS (C4) Pull-down to 0V General Purpose Input or Transmit serial data (UART2) Not connected I/O CMOS/ CMOS 1X Pull-down to 0V Keyboard Row Not connected 20 GPO2 or CT104/RXD2 O CMOS 3X (C1) or CMOS 1X (C1) 2V8 General Purpose Output or Receive serial data (UART2) Not connected 21 ROW4 I/O CMOS/ CMOS 1X Pull-down to 0V Keyboard Row Not connected 22 GPO1 O CM
Wireless CPU Q24 Series Technical Specifications Pin Name 35 36 37 38 GPIO5 or CT105/RTS2 CT107/DSR1 CT106/CTS1 BAT_TEMP I/O I/O type Reset state Description I/O CMOS/CMOS 2X (C1) or CMOS I High impedance General Purpose I/O or Clear To Send (UART2) Not connected Dealing with unused pins O CMOS 1X (C3) 2V8 Data Set Ready (UART1) Not connected O CMOS 1X (C1) High impedance Clear To Send (UART1) Test point (Download purposes) Analog High impedance ADC input for battery temperature m
Wireless CPU Q24 Series Technical Specifications Pin Name 54 GPIO2 or CT125 / RI1 55 +VBATT I/O I/O type Reset state I/O CMOS/CMOS 2X (C1) or CMOS 2X O (C1) High impedance General Purpose I/O or Ring Indicator (UART1) Not connected - Battery Input Must be used Not connected I Supply Description Dealing with unused pins 56 VCC_RTC I/O Supply 2V8 RTC back-up supply 57 +VBATT I Supply - Battery Input Must be used 58 +VBATT I Supply - Battery Input Must be used 59 +VBATT
Wireless CPU Q24 Series Technical Specifications 4.2 I/O Circuit Diagram The following drawings show the internal interface of the Wireless CPU Q24 Series. The type indication per interface can be found in the previous chapters.
Wireless CPU Q24 Series Environmental Specifications 5 Environmental Specifications The Wireless CPU Q24 Classic and Q24 Plus are compliant with the following operating classes: Condition Operating / Class A Storage Temperature range -20°C to +55°C for GSM 850 / 900 -10°C to +55°C for GSM 1800/1900 -40°C to +85°C The Wireless CPU Q24 Automotive and Q24 Extended are compliant with the following operating classes: Conditions Operating / Class A Temperature range -20°C to +55°Cfor GSM 850 / 900 -10°C to +5
Wireless CPU Q24 Series Environmental Specifications 5.1 Environmental Qualifications For the Wireless CPU Q24 Classic, Q24 Plus, and Q24 environmental qualifications are defined in the table below: Extended, applied ENVIRONMENTAL CLASSES TYPE OF TEST STANDARDS STORAGE Class 1.2 TRANSPORTATION Class 2.3 Cold IEC 68-2.1 Ab test -25° C 72 h -40° C 72 h -20° C (GSM900) -10° C (GSM1800/1900) 16 h 16h Dry heat IEC 68-2.
Wireless CPU Q24 Series Environmental Specifications For the Wireless CPU Q24 Automotive, environmental qualification applied is defined in table below: Test Designation Standards Resistance to Heat IEC 60068-2-2 Resistance to cold test IEC 60068-2-30 Db Cooking Test - Damp heat test IEC 60068-2-3 Damp heat cycle test IEC 60068-2-30 Db Temperature change IEC 60068-2-14 Nb Thermal Shock IEC 60068-2-14 Resistance IEC 60068-2-6 Fc to sinusoidal vibration Resistance to random vibration IEC 600
Wireless CPU Q24 Series Environmental Specifications 5.2 Mechanical Specifications 5.2.1 Physical Characteristics The Wireless CPU Q24NG sub-series have a complete self-contained shield. • Dimensions : 58.4 x 32.2 x 3.9 mm external dimensions (excluding shielding pins) • Weight : <11 g (12g for Q24 Automotive) 5.2.2 Mechanical Drawings The following page gives the mechanical specifications of the Wireless CPU Q24 Series. Figure 18: Mechanical drawing.
Wireless CPU Q24 Series Connector and Peripheral Device References 6 Connector and Peripheral Device References 6.1 General Purpose Connector Data Sheet The supplier for the http://www.avxcorp.com. GPC connector is KYOCERA/ELCO, available from Ref: 14 5087 060 930 861, or 19 5087 060 930 861. 6.2 SIM Card Reader These SIM Card holder references may be used in customer application with Wireless CPU Q24 version, not already equipped with a SIM Card holder. • ITT CANNON CCM03 series (see http://www.
Wireless CPU Q24 Series Connector and Peripheral Device References 6.6 RF board-to-board Connector The supplier for the IMP connector is Radiall (http://www.radiall.com) with the following references: • R107 064 900. • R107 064 920. The supplier for the MMS connector is Radiall (http://www.radiall.com) 6.7 GSM Antenna GSM antenna and support for antenna adaptation may be obtained from the manufacturers such as: • ALLGON (http://www.allgon.com) • HIRSCHMANN (http://www.hirschmann.
Wireless CPU Q24 Series Appendix 7 Appendix 7.1 Standards and Recommendations GSM ETSI, 3GPP, GCF, and NAPRD03 recommendations for Phase II. Specification Reference 3GPP TS 45.005 v5.5.0 (2002-08) Release 5 GSM 02.07 V8.0.0 (1999-07) GSM 02.60 V8.1.0 (1999-07) GSM 03.60 V7.9.0 (2002-09) 3GPP TS 43.064 V5.0.0 (2002-04) 3GPP TS 03.22 V8.7.0 (2002-08) 3GPP TS 03.40 V7.5.0 (2001-12) 3GPP TS 03.41 V7.4.0 (2000-09) ETSI EN 300 903 V8.1.1 (2000-11) 3GPP TS 04.06 V8.2.
Wireless CPU Q24 Series Appendix Specification Reference 3GPP TS 04.08 V7.18.0 (2002-09) 3GPP TS 04.10 V7.1.0 (2001-12) 3GPP TS 04.11 V7.1.0 (2000-09) 3GPP TS 45.005 v5.5.0 (2002-08) 3GPP TS 45.008 V5.8.0 (2002-08) 3GPP TS 45.010 V5.1.0 (2002-08) 3GPP TS 46.010 V5.0.0 (2002-06) 3GPP TS 46.011 V5.0.0 (2002-06) 3GPP TS 46.012 V5.0.0 (2002-06) 3GPP TS 46.031 V5.0.0 (2002-06) 3GPP TS 46.032 V5.0.0 (2002-06) TS 100 913V8.0.
Wireless CPU Q24 Series Appendix Specification Reference GSM 09.07 V8.0.0 (1999-08) 3GPP TS 51.010-1 v7.3.1 (2006-10) 3GPP TS 51.011 V5.0.0 (2001-12) ETS 300 641 (1998-03) GCF-CC V3.23.1 (2006-07) NAPRD03 v3.8.1 (2006-08) Title Digital cellular telecommunications system (Phase 2+); General requirements on inter-working between the Public Land Mobile Network (PLMN) and the Integrated Services Digital Network (ISDN) or Public Switched Telephone Network (PSTN) (GSM 09.07 version 8.0.
Wireless CPU Q24 Series Appendix The license module will have a FCC ID label on the module itself. The FCC ID label must be visible through a window or it must be visible when an access panel, door or cover is easily removed.
Wireless CPU Q24 Series Appendix 7.2.1.2 Exposure to RF Energy There has been some public concern on possible health effects of using GSM terminals. Although research on health effects from RF energy has focused on the current RF technology for many years, scientists have begun research regarding newer radio technologies, such as GSM. After existing research had been reviewed, and after compliance to all applicable safety standards had been tested, it has been concluded that the product was safe to use.
Wireless CPU Q24 Series Appendix 7.2.2.2 Electronic Devices Most electronic equipments, for example in hospitals and motor vehicles are shielded from RF energy. However, RF energy may affect some improperly shielded electronic equipment. 7.2.2.3 Vehicle Electronic Equipment Check with your vehicle manufacturer/representative to determine if any on-board electronic equipment is adequately shielded from RF energy. 7.2.2.
Wireless CPU Q24 Series Appendix fuel or chemical transfer or storage facilities; and areas where the air contains chemicals or particles, such as grain, dust, or metal powders. Do not transport or store flammable gas, liquid, or explosives, in the compartment of your vehicle, which contains your terminal or accessories.
WAVECOM S.A. - 3 esplanade du Foncet - 92442 Issy-les-Moulineaux Cedex - France - Tel: +33(0)1 46 29 08 00 - Fax: +33(0)1 46 29 08 08 Wavecom, Inc. - 4810 Eastgate Mall - Second Floor - San Diego, CA 92121 - USA - Tel: +1 858 362 0101 - Fax: +1 858 558 5485 WAVECOM Asia Pacific Ltd. - Unit 201-207, 2nd Floor, Bio-Informatics Centre – No.
